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參數(shù)資料
| 型號(hào)： | IDT29FCT520APB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | MULTILEVEL PIPELINE REGISTER |
| 中文描述： | 多級(jí)管道注冊(cè) |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 58K |
| 代理商： | IDT29FCT520APB |
7.2
2
IDT29FCT520A/B/C
MULTILEVEL PIPELINE REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
I
0
2620 drw 02
5
6
7
8
9
10
11
L28-1
25
24
23
22
21
20
19
INDEX
D
1
D
2
D
3
NC
D
4
D
5
D
6
N
V
S
0
S
1
D
0
I
1
G
N
NC
Y
3
Y
4
Y
5
Y
0
Y
1
Y
2
D
7
C
O
Y
6
Y
7
12 13 14 15 16 17 18
4
3
2
1
28 27 26
DIP/CERPACK/SOIC
TOP VIEW
5
6
7
8
9
10
11
12
GND
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
S
0
S
1
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
P24-1,
D24-1,
E24-1
&
SO24-2
OE
I
0
I
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CLK
LCC
TOP VIEW
DEFINITION OF FUNCTIONAL TERMS
Pin Names
D
n
Register input port.
CLK
Clock input. Enter data into registers on LOW-
to-HIGH transitions.
I
0
, I
1
Instruction inputs. See Figure 1 and In-
struction Control Tables.
S
0
, S
1
Multiplexer select. Inputs either register A
1
, A
2
,
B
1
or B
2
data to be available at the output port.
OE
Output enable for 3-state output port
Y
n
Register output port.
Description
2620 tbl 01
REGISTER SELECTION
S
1
0
0
1
1
S
0
0
1
0
1
Register
B
2
B
1
A
2
A
1
2620 tbl 02
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PDF描述 |
|---|---|
| IDT29FCT520BPB | MULTILEVEL PIPELINE REGISTER |
| IDT29FCT52ASOB | FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
| IDT29FCT53ASOB | FAST CMOS OCTAL REGISTERED TRANSCEIVERS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT29FCT520ASO | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:MULTILEVEL PIPELINE REGISTER |
| IDT29FCT520ASOB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:MULTILEVEL PIPELINE REGISTER |
| IDT29FCT520AT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:MULTILEVEL PIPELINE REGISTERS |
| IDT29FCT520ATP | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT29FCT520ATPY | 制造商:Integrated Device Technology Inc 功能描述: |
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