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參數(shù)資料
| 型號(hào)： | IDT23S08T-1DCG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK MULT PLL ZD 2.5V 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類(lèi)型： | 時(shí)鐘倍頻器，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | LVTTL |
| 輸出： | LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:8 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 133.3MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | 23S08T-1DCG8 |
3
COMMERCIALTEMPERATURERANGE
IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
S2
S1
CLK A
CLK B
Output Source
PLL Shut Down
L
Tri-State
PLL
Y
L
H
Driven
Tri-State
PLL
N
H
L
Driven
REF
Y
H
Driven
PLL
N
FUNCTION TABLE(1) SELECT INPUT DECODING
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
SPREAD SPECTRUM COMPATIBLE
Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter
off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.
Device
Feedback From
Bank A Frequency
Bank B Frequency
IDT23S08T-1
Bank A or Bank B
Reference
IDT23S08T-2(1)
Bank A
Reference
Reference/2
IDT23S08T-2(1)
Bank B
2 x Reference
Reference
IDT23S08T-3(1)
Bank A
2 x Reference
Reference or
Reference(2)
IDT23S08T-3(1)
Bank B
4 x Reference
2 x Reference
IDT23S08T-4(1)
Bank A or Bank B
2 x Reference
IDT23S08T-5(1)
Bank A or Bank B
Reference/2
NOTES:
1. Contact factory for availability.
2. Output phase is indeterminant (0° or 180° from input clock).
AVAILABLE OPTIONS FOR IDT23S08T
ZERO DELAY AND SKEW CONTROL
To close the feedback loop of the IDT23S08T, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are
loaded equally, for zero output-output skew.
NOTE:
1. Applies to both REF and FBK.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VDD
Supply Voltage
2.3
2.7
V
TA
OperatingTemperature(AmbientTemperature)
0
70
° C
CL
Load Capacitance from 10MHz to 133MHz
—
15
pF
CIN
InputCapacitance(1)
—7
pF
OPERATING CONDITIONS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT23S08T-2 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S08T-2DC | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S08T-3 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S08T-3DC | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S08T-4 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
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