參數(shù)資料
型號(hào): IDT2308A-3DCI8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 4/10頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK MULT ZD STD DRV 16-SOIC
產(chǎn)品變化通告: Product Discontinuation 13/May/2009
標(biāo)準(zhǔn)包裝: 2,500
類(lèi)型: 倍增器,零延遲緩沖器
PLL: 帶旁路
輸入: LVTTL
輸出: LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 133.3MHz
除法器/乘法器: 無(wú)/是
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 帶卷 (TR)
其它名稱(chēng): 2308A-3DCI8
3
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
Device
FeedbackFrom
Bank A Frequency
Bank B Frequency
IDT2308A-1
Bank A or Bank B
Reference
IDT2308A-1H
Bank A or Bank B
Reference
IDT2308A-2
Bank A
Reference
Reference/2
IDT2308A-2
Bank B
2 x Reference
Reference
IDT2308A-2H
Bank A
Reference
Reference/2
IDT2308A-2H
Bank B
2 x Reference
Reference
IDT2308A-3
Bank A
2 x Reference
Reference or Reference(1)
IDT2308A-3
Bank B
4 x Reference
2 x Reference
IDT2308A-4
Bank A or Bank B
2 x Reference
NOTE:
1. Output phase is indeterminant (0° or 180° from input clock).
AVAILABLE OPTIONS FOR IDT2308A
S2
S1
CLK A
CLK B
Output Source
PLL Shut Down
L
Tri-State
PLL
Y
L
H
Driven
Tri-State
PLL
N
H
L
Driven
REF
Y
H
Driven
PLL
N
FUNCTION TABLE(1) SELECT INPUT DECODING
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
ZERO DELAYAND SKEW CONTROL
To close the feedback loop of the IDT2308A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are
loaded equally, for zero output-output skew.
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