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參數(shù)資料
| 型號： | IDT2308A-2HDCI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 70K |
| 代理商： | IDT2308A-2HDCI8 |
3
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
Device
Feedback From
Bank A Frequency
Bank B Frequency
IDT2308A-1
Bank A or Bank B
Reference
IDT2308A-1H
Bank A or Bank B
Reference
IDT2308A-2
Bank A
Reference
Reference/2
IDT2308A-2
Bank B
2 x Reference
Reference
IDT2308A-2H
Bank A
Reference
Reference/2
IDT2308A-2H
Bank B
2 x Reference
Reference
IDT2308A-3
Bank A
2 x Reference
Reference or
Reference(1)
IDT2308A-3
Bank B
4 x Reference
2 x Reference
IDT2308A-4
Bank A or Bank B
2 x Reference
NOTE:
1. Output phase is indeterminant (0° or 180° from input clock).
AVAILABLE OPTIONS FOR IDT2308A
S2
S1
CLK A
CLK B
Output Source
PLL Shut Down
L
Tri-State
PLL
Y
L
H
Driven
Tri-State
PLL
N
H
L
Driven
REF
Y
H
Driven
PLL
N
FUNCTION TABLE(1) SELECT INPUT DECODING
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
ZERO DELAY AND SKEW CONTROL
To close the feedback loop of the IDT2308A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are
loaded equally, for zero output-output skew.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT2308A-1DCGI8 | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| IDT2308A-1DCG8 | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| IDT2308A-4DCG8 | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| IDT2308A-1HPGI8 | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| IDT2308A-1DC8 | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT2308A-2HPG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2HPGG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2HPGGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2HPGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2PG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V ZERO DELAY CLOCK MULTIPLIER |
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