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參數(shù)資料
| 型號(hào)： | ICSSSTVA16859BG-T |
| 英文描述： | DDR 13-Bit to 26-Bit Registered Buffer |
| 中文描述： | 復(fù)員13位至26位注冊(cè)緩沖區(qū) |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大小： | 135K |
| 代理商： | ICSSSTVA16859BG-T |
ICSSSTVA16859B
1050A—01/07/05
Notes:
1. CL incluces probe and jig capacitance.
2. I
DD
tested with clock and data inputs held at V
DDQ
or GND, and I
O
= 0 mA.
3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz,
Zo=50
, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. V
TT
= V
REF
= V
DDQ
/2
6. V
IH
= V
REF
+ 310mV (AC voltage levels) for differential inputs. V
IH
= V
DDQ
for LVCMOS input.
7. V
IL
= V
REF
- 310mV (AC voltage levels) for differential inputs. V
IL
= GND for LVCMOS input.
8. t
PLH
and t
PHL
are the same as t
pd
C
= 30 pF
(see Note 1)
From Output
Under Test
Load Circuit
1k
LVCMOS
RESET#
Input
LVCMOS
RESET#
Input
V
DDQ
/2
V
DDQ
/2
t
inact
t
act
I
(see note 2)
DD
I
DDH
I
DDL
10%
90%
Voltage and Current Waveforms
Inputs Active and Inactive Times
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Propagation Delay Times
Figure 1 - Parameter Measurement Information (V
DDQ
= 2.5V ±0.2V)
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
V
DDQ
0 V
t
w
t
S
t
h
V
IH
V
IH
V
OH
V
TT
V
TT
V
TT
V
OH
V
IH
V
IL
V
IL
V
OL
V
OL
V
I(pp)
V
I(pp)
V
IL
V
REF
V
REF
V
REF
V
REF
V
ICR
V
ICR
t
PHL
t
PHL
t
PHL
V
/2
DD
V
ICR
Input
Input
Timing
Input
Timing
Input
Output
Output
1k
Test point
V
DD
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相關(guān)代理商/技術(shù)參數(shù) |
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