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參數(shù)資料
| 型號： | ICSSSTV16859yG-T |
| 英文描述： | DDR 13-Bit to 26-Bit Registered Buffer |
| 中文描述： | 復員13位至26位注冊緩沖區(qū) |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 100K |
| 代理商： | ICSSSTV16859YG-T |
5
ICSSSTV16859
0003G—05/21/02
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
From
(Input)
(Output)
MIN
200
1.7
1.6
TYP
MAX
f
max
MHz
ns
ns
ns
CLK, CLK# (TSSOP)
CLK, CLK# (VFQFN[MLF2])
RESET#
Q
Q
Q
2.3
2.1
2.7
2.6
5
t
phl
SYMBOL
V
DD
= 2.5V ±0.2V
UNITS
To
t
PD
Timing Requirements
1
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
200
2.7
2.6
5
4
f
clock
Clock frequency
MHz
ns
ns
ns
V/ns
ns
ns
ns
ns
TSSOP
VFQFN (MLF2)
1.7
1.6
t
RST
t
SL
Reset to output time
Output slew rate
Setup time, fast slew rate
2 & 4
Setup time, slow slew rate
3 & 4
Hold time, fast slew rate
2 & 4
Hold time, slow slew rate
3 & 4
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of
≥
1V/ns.
3 - For data signal input slew rate of
≥
0.5V/ns and < 1V/ns.
1
0.60
0.80
0.40
0.50
4 - CLK, CLK# signals input slew rate of
≥
1V/ns.
SYMBOL
t
S
T
h
Notes:
t
PD
V
DDQ
= 2.5V ± 0.2V
UNITS
PARAMETERS
Data before CLK
↑
, CLK#
↓
Data after CLK
↑
, CLK#
↓
Clock to output time
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICSSSTV16859YK | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV32852 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 24-Bit to 48-Bit Registered Buffer |
| ICSSSTV32852YHT | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 24-Bit to 48-Bit Registered Buffer |
| ICSSSTVA16857 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTVA16857YGLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
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