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參數(shù)資料
| 型號(hào)： | ICSSSTUB32872A |
| 英文描述： | 28-Bit Registered Buffer for DDR2 |
| 中文描述： | 28位注冊緩沖DDR2內(nèi)存 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 222K |
| 代理商： | ICSSSTUB32872A |
12
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
410
f
clock
t
W
t
ACT
Clock frequency
Pulse duration
Differential inputs active time
MHz
ns
ns
1
10
t
INACT
Differential inputs inactive time
15
ns
t
S
Data before CK
↑
,
CK
↓
DCS0
,
DSC1
before CK
↑
,
CK
↓
,
CSR
high
DCS
, DODT, DCKE and Dn
after CK
↑
,
CK
↓
0.6
0.7
Hold time
0.6
ns
Hold time
PAR_IN after CK
↑
,
CK
↓
0.5
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CK/
CK
signal input slew rate of 1V/ns.
SYMBOL
Notes:
t
H
V
DD
= 1.8V ±0.1V
UNITS
PARAMETERS
ns
Setup time
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement Conditions
MIN
MAX
Units
fmax
Max input clock frequency
410
MHz
t
PDM
Propagation delay, single
bit switching
Low to High propagation
delay
High to low propagation
delay
Propagation delay
simultaneous switching
High to low propagation
delay
Low to High propagation
delay
1. Guaranteed by design, not 100% tested in production.
CK
↑
and
CK
↓
to Qn
1.25
1.9
ns
t
LH
1.2
3
ns
t
HL
0.9
3
ns
t
PDMSS
CK
↑
and
CK
↓
to Qn
2
ns
t
PHL
RESET
↓
to Qn
↓
3
ns
t
PLH
RESE
T
↓
to
PTYERR
↑
3
ns
CK
↑
and
CK
↓
to
PTYERR
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| ICSSSTUBF32866A | 25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUBF32866Az(LF)T | 25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUF32864A | 25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUF32864AYHLF-T | 25-Bit Configurable Registered Buffer for DDR2 |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ICSSSTUBF32866A | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUBF32866AZ(LF)T | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUF32864A | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUF32864AYHLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTV16857 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
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