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參數(shù)資料
| 型號： | ICSSSTUB32864A |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 25-Bit Configurable Registered Buffer for DDR2 |
| 中文描述： | 25位可配置的注冊緩沖DDR2內(nèi)存 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 152K |
| 代理商： | ICSSSTUB32864A |
ICSSSTUB32864A
Advance Information
1166—10/05/05
8
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
f
clock
Clock frequency
t
W
t
ACT
t
INACT
Differential inputs inactive time (See notes 1 and 3)
MIN
MAX
410
UNITS
MHz
ns
ns
ns
1
10
15
Setup time
DCS before CK, CK
↓
,
CSR high; CSR before
CK, CK
↓
, DCS high
DCS before CK, CK
↓
,
CSR Low
DODT, DCKE and data
before CK, CK
↓
DCS, DODT, DCKE and
data after CK, CK
↓
PAR_IN after CK, CK
↓
0.6
ns
0.5
ns
0.5
ns
0.4
ns
0.4
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
Pulse duration, CK, CK High or Low
Differential inputs active time (See notes 1 and 2)
Hold time
t
SU
t
h
Notes:
Setup time
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
From
(Input)
(Output)
MIN
410
1.1
TYP
MAX
fmax
t
PDM1
t
PDMSS2
t
phl
Notes: 1. Includes 350ps test-load transmission-line delay
2. Guaranteed by design, not 100% tested in production.
MHz
ns
CLK, CLK#
CLK, CLK#
RESET#
Q
Q
Q
1.5
1.6
3
ns
SYMBOL
V
DD
= 1.8V ±0.1V
UNITS
To
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
V
DD
= 1.8V ± 0.1V
MIN
1
1
MAX
4
4
1
dV/dt_r
dV/dt_f
dV/dt_
1
V/ns
V/ns
V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER
UNIT
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