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參數(shù)資料
| 型號： | ICSSSTUAH32868A |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | 28位可配置注冊緩沖內(nèi)存 |
| 文件頁數(shù)： | 15/22頁 |
| 文件大小： | 468K |
| 代理商： | ICSSSTUAH32868A |
ICSSSTUAH32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
15
ICSSSTUAH32868A
7115/9
Register Timing
NOTES:
1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held LOW for a
minimum time of t
ACTMAX
, to avoid false error.
2.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and
it will be valid on the n+3 clock pulse.
n
n +1
n + 2
n + 3
n + 4
t
PDM,
t
PDMSS
CLK to Q
t
SU
CLK
CLK
Dn, DODTn,
DCKEn
PARIN
QERR
Qn, QODTn,
QCKEn
t
PHL
t
SU
t
H
t
ACT
t
H
Data to QERR Latency
CLK to QERR
CLK to QERR
t
PHL,
t
PLH
DCS1
DCS0
CSGEN
RESET
H, L, or X
H or L
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ICSSSTUAH32868AHLF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUB32864A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUB32864AZ(LF)T | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUB32866B | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUB32866BZ(LF)T | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
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