
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
1626
09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
7
Advance Information
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA =Over the Specified Operating Range; VDD = 3.3 V +/-5%; CL =2pF, RS=33 , RP=49.9 , RREF=475
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Current Source Output
Impedance
Zo
1
3000
1
Voltage High
VHigh
660
850
1,2
Voltage Low
VLow
-150
150
1,2
Max Voltage
Vovs
1150
1
Min Voltage
Vuds
-300
1
Crossing Voltage (abs)
Vcross(ab
s)
250
550
mV
1
Crossing Voltage (var)
d-Vcross
Variation of crossing over all edges
140
mV
1
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
1
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-tr
125
ps
1
Fall Time Variation
d-tf
125
ps
1
Duty Cycle
dt3
Measurement from differential wavefrom
45
55
%
1
tpdBYP
Bypass Mode, VT = 50%
2500
4500
ps
1
tpdPLL
PLL Mode VT = 50%, Spread Off
-250
250
ps
1
Skew, Output to Output
tsk3
VT = 50%
50
ps
1
PLL mode
50
ps
1,3
Additive
Jitter in Bypass Mode
50
ps
1,3
PCIe Gen1 phase jitter
(Additive in Bypass Mode)
10
ps
(pk2pk)
1,4,5
PCIe Gen 2 Low Band phase jitter
(Additive in Bypass Mode)
0.1
ps
(rms)
1,4,5
PCIe Gen 2 High Band phase jitter
(Additive in Bypass Mode)
0.5
ps
(rms)
1,4,5
PCIe Gen 1 phase jitter
86
ps
(pk2pk)
1,4,5
PCIe Gen 2 Low Band phase jitter
3
ps
(rms)
1,4,5
PCIe Gen 2 High Band phase jitter
3.1
ps
(rms)
1,4,5
1Guaranteed by design and characterization, not 100% tested in production.
2 I
REF = VDD/(3xRR). For RR = 475
(1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 .
3 Measured from differential waveform
4 See http://www.pcisig.com for complete specs
5 Device driven by 932S421C or equivalent.
Statistical measurement on single ended
signal using oscilloscope math function.
mV
Measurement on single ended signal
using absolute value.
mV
Skew, Input to Output
Jitter, Cycle to cycle
tjcyc-cyc
Jitter, Phase
tjphaseBYP
tjphasePLL