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參數(shù)資料
| 型號(hào)： | ICS9DB801CGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Eight Output Differential Buffer for PCI Express (50-200MHz) |
| 中文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 215K |
| 代理商： | ICS9DB801CGLFT |
IDT
TM
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz)
ICS9DB801C REV C 08/16/07
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
4
Pin Description for OE_INV = 0
PIN #
PIN NAME
25
GND
PIN TYPE
POWER
DESCRIPTION
Ground pin.
Asynchronous active low input pin, with 120Kohm internal pull-
up resistor, used to power down the device. The internal clocks
are disabled and the VCO and the crystal are stopped.
Active low input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
26
PD#
INPUT
27
SRC_STOP#
INPUT
28
HIGH_BW#
INPUT
29
30
31
32
33
34
DIF_4#
DIF_4
VDD
GND
DIF_5#
DIF_5
OUTPUT
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
35
OE_5
INPUT
36
OE_6
INPUT
37
38
39
DIF_6#
DIF_6
VDD
OUTPUT
OUTPUT
POWER
40
OE_INV
INPUT
41
42
DIF_7#
DIF_7
OUTPUT
OUTPUT
43
OE_4
INPUT
44
OE_7
INPUT
45
LOCK
OUTPUT
46
IREF
INPUT
47
48
GNDA
VDDA
POWER
POWER
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9DB803DFILF | 制造商:Integrated Device Technology Inc 功能描述:IC BUFFER 8OUTPUT DIFF 48-SSOP |
| ICS9DB803DFILFT | 制造商:Integrated Device Technology Inc 功能描述:IC BUFFER 8OUTPUT DIFF 48-SSOP |
| ICS9DB803DFLF | 功能描述:IC BUFFER 8OUTPUT DIFF 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| ICS9DB803DFLFT | 功能描述:IC BUFFER 8OUTPUT DIFF 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| ICS9DB803DGILF | 功能描述:IC BUFFER 8OUTPUT DIFF 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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