參數(shù)資料
型號: ICS9DB106YGLF-T
英文描述: 6 Output PCI Express Buffer with CLKREQ Function
中文描述: 6輸出的PCI Express功能的緩沖與CLKREQ
文件頁數(shù): 5/9頁
文件大小: 118K
代理商: ICS9DB106YGLF-T
5
Integrated
Circuit
Systems, Inc.
ICS9DB106
Preliminary Product Preview
0833A—07/26/04
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Outputs
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
η
, R
P
=49.9
ηΡ
REF
ηΡ 9,
PARAMETER
SYMBOL
Current Source Output
Impedance
Statistical measurement on
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Zo
1
V
O
= V
x
3000
η
1
Voltage High
VHigh
660
850
1,3
Voltage Low
VLow
-150
150
1,3
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
1150
1,3
1,3
1,3
-300
250
Vcross(abs)
550
mV
Crossing Voltage (var)
d-Vcross
Variation of crossing over all
edges
see Tperiod min-max values
100.00MHz nominal
100.00MHz spread
100.00MHz nominal/spread
V
OL
= 0.175V, V
OH
= 0.525V
V
OH
= 0.525V V
OL
= 0.175V
140
mV
1,3
Long Accuracy
ppm
0
ppm
ns
ns
ns
ps
ps
ps
ps
ps
ns
1,2
2
2
1,2
1
1
1
1
1
1
9.9970
9.9970
9.8720
175
175
10.0030
10.0533
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
T
absmin
t
r
t
f
d-t
r
d-t
f
t
pd
t
pdbyp
700
700
125
125
150
3.7
PLL Mode.
Bypass mode
100
3.2
Duty Cycle
d
t3
Measurement from differential
wavefrom
V
T
= 50%
PLL mode,
Measurement from differential
wavefrom
BYPASS mode as additive jitter
45
55
%
1
Output-to-Output Skew
t
sk3
30
ps
1
40
ps
1
25
ps
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock
complies with CK409/CK410 accuracy requirements
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
η
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
η
.
Jitter, Cycle to cycle
t
jcyc-cyc
Average period
T
period
Input to Output Delay
single ended signal using
oscilloscope math function.
mV
Measurement on single ended
signal using absolute value.
mV
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