參數(shù)資料
型號: ICS954201YGLNT
英文描述: Programmable Timing Control Hub⑩ for Mobile P4⑩ Systems
中文描述: 可編程定時控制中心,對移動P4⑩⑩系統(tǒng)
文件頁數(shù): 3/15頁
文件大?。?/td> 157K
代理商: ICS954201YGLNT
3
Integrated
Circuit
Systems, Inc.
ICS954201
0819G—12/06/04
Pin Description (Continued)
PIN # PIN NAME
29
GND
30
SRCCLKC5
31
SRCCLKT5
32
SRCCLKC6
33
SRCCLKT6
34
VDDSRC
TYPE
PWR
OUT
OUT
OUT
OUT
PWR
DESCRIPTION
Ground pin.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Complimentary clock of CPU_ITP/SRC differential pair
CPU_ITP/SRC output. These are current mode outputs.
External resistors are required for voltage bias. Selected by
ITP_EN input.
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are
required for voltage bias. Selected by ITP_EN input.
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
True clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
True clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
Reference Clock output
3.3V tolerant input for CPU frequency selection. Low voltage
threshold inputs, see input electrical characteristics for Vil_FS
and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
Stops all CPUCLK, except those set to be free running clocks
35
CPUCLKC2_ITP/SRCCLKC7
OUT
36
CPUCLKT2_ITP/SRCCLKT7
OUT
37
38
VDDA
GNDA
PWR
PWR
39
IREF
OUT
40
CPUCLKC1
OUT
41
CPUCLKT1
OUT
42
VDDCPU
PWR
43
CPUCLKC0
OUT
44
CPUCLKT0
OUT
45
46
47
48
49
50
51
52
GND
SCLK
SDATA
VDDREF
X2
X1
GND
REFOUT
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
53
FS_C/TEST_SEL
IN
54
CPU_STOP#
IN
55
PCI/SRC_STOP#
IN
Stops all PCICLKs and SRCCLKs besides the free-running
clocks at logic 0 level, when input low
PCI clock output.
56
PCICLK2
OUT
相關(guān)PDF資料
PDF描述
ICS954201YFLNT Programmable Timing Control Hub⑩ for Mobile P4⑩ Systems
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ICS954204 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85
ICS95420YGLFT Filter Module
ICS95420YGLNT Filter Module with Resistor Network
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