參數(shù)資料
型號(hào): ICS952801yFT
英文描述: Programmable Timing Control HubTM for K8TM processor
中文描述: 可編程定時(shí)控制HubTM處理器K8TM
文件頁數(shù): 9/22頁
文件大?。?/td> 191K
代理商: ICS952801YFT
9
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
0719—01/22/03
I
2
C Table: Function Control Register
Control
Function
PD# Enable
Output Control
WD Soft Enable
Output Control
Async Rom SEL_1
Async Rom SEL_0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PDEN
PCICLK7
WDS_EN
PCICLK6
AFS1
AFS0
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
See Table 3: Async Z-CLK
Frequency Selection Table
Enable
Enable
Enable
Enable
1
1
1
1
0
0
Bit 1
AEN1
RW
0
Bit 0
AEN0
RW
0
Zclk/Agp/Pci Freq
Source Select Control
See Table 4 : ZCLK, AGP &
PCI Frequency Source
Decode Table
-
-
-
25
-
-
1
PWD
-
26
Name
Pin #
Byte 0
Type
0
Table 3: Asynchronous ZCLK Frequency Selection Table
Byte0 Bit3
Byte0 Bit2
ZCLK Frequency
Table 4: ZCLK, AGP & PCI Frequency Source Decode Table
Byte0 Bit1
Byte0 Bit0
ZCLK & AGP & PCI
See Table 1, QuadRom
Frequency Table
N-Programming for
AGP/PCI/ZCLK
See Table 1 for AGP/PCI,
Table 3 for ZCLK
0
0
64.01
0
0
0
1
72.01
0
1
1
0
82.30
1
0
1
1
144.02
1
1
N-Programming for AGP/PCI,
Table 3 for ZCLK
I
2
C Table: Async N-Programming Frequency Select Register
Control
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N PLL3 Div7
N PLL3 Div6
N PLL3 Div5
N PLL3 Div4
N PLL3 Div3
N PLL3 Div2
N PLL3 Div1
N PLL3 Div0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
1
0
0
0
1
1
1
I
2
C Table: Reserved Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
The decimal
representation of N
PLL2 Div (7:0) + 8 is
equal to VCO divider
value for PLL2. Default
at power up =
66.67MHz
-
-
-
Name
-
-
-
-
1
1
PWD
0
Type
PWD
0
-
-
-
-
Name
Type
Byte 2
-
Pin #
Pin #
-
-
Byte 1
-
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