
3
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
0719—01/22/03
Pin Description
PIN
PIN
PIN
#
NAME
TYPE
1
2
3
4
5
6
7
8
9
10
11
VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
PWR Ground pin for the REF outputs.
IN
Crystal input,nominally 14.318MHz.
OUT Crystal output, Nominally 14.318MHz
PWR Ground pin for the ZCLK outputs
OUT 3.3V Hyperzip clock output.
OUT 3.3V Hyperzip clock output.
PWR Power supply for ZCLK clocks, nominal 3.3V
PCI clock output, this output is activated by the Mode selection pin / Stops all PCICLKs
besides the PCICLK_F clocks at logic 0 level, when input low.
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
PWR Power supply for PCI clocks, nominal 3.3V
PWR Ground pin for the PCI outputs
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin for the PCI outputs
PWR Power supply for PCI clocks, nominal 3.3V
OUT PCI clock output.
OUT PCI clock output.
I/O
Data pin for I2C circuitry 5V tolerant
PWR Ground pin for the 48MHz outputs
24/48MHz clock output / Latched select input for 24/48MHz output. 0=24mHz, 1 =
48MHz.
OUT 48MHz clock output.
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
IN
Clock pin of I2C circuitry 5V tolerant
PWR Power supply for AGP clocks, nominal 3.3V
OUT AGP clock output
OUT AGP clock output
PWR Ground pin for the AGP outputs
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 1.8ms.
PWR 3.3V Analog Power pin for Core PLL
PWR Analog Ground pin for Core PLL
PWR Ground pin for the CPU outputs
OUT "Complementary" clocks of differential 3.3V push-pull K8 pair.
OUT "True" clocks of differential 3.3V push-pull K8 pair.
PWR Supply for CPU clocks, 3.3V nominal
PWR Supply for CPU clocks, 3.3V nominal
OUT "Complementary" clocks of differential 3.3V push-pull K8 pair.
OUT "True" clocks of differential 3.3V push-pull K8 pair.
PWR Ground pin for the CPU outputs
IN
Stops all CPUCLK besides the free running clocks
** Internal Pull-Down Resistor
**FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
12
*PCI_STOP#
**FS3/PCICLK_F0
**FS4/PCICLK_F1
VDDPCI
GNDPCI
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
VDDPCI
PCICLK6
PCICLK7
SDATA
GND48
I/O
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
24_48MHz/SEL24_48MHz*
I/O
30
31
32
33
34
35
36
48MHz
AVDD48
SCLK
VDDAGP
AGPCLK1
AGPCLK0
GNDAGP
37
PD#*
IN
38
39
40
41
42
43
44
45
46
47
48
* Internal Pull-Up Resistor
AVDD
AGND
GNDCPU
CPUCLK8C0
CPUCLK8T0
VDDCPU
VDDCPU
CPUCLK8C1
CPUCLK8T1
GNDCPU
CPU_STOP#*
DESCRIPTION