參數(shù)資料
型號: ICS952703
英文描述: Programmable Timing Control Hub for K7 System
中文描述: 可編程定時控制中心的k7的系統(tǒng)
文件頁數(shù): 3/17頁
文件大小: 143K
代理商: ICS952703
3
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
0813B—05/17/05
Pin Description
PIN # PIN NAME
PIN
TYPE
PWR
I/O
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
PWR
IN
PWR
I/O
I/O
OUT
OUT
PWR
PWR
OUT
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VDDREF
**FS0/REF0
**FS1/REF1
**Mode/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
SCLK
VDDPCI
*FS2/PCICLK_F0
*FS3/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
Ref, XTAL power supply, nominal 3.3V
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Function select latch input pin, 0=Desktop Mode, 1=Mobile Mode / Ref clock output.
Ground pin for the REF outputs.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin for the ZCLK outputs
3.3V Hyperzip clock output.
3.3V Hyperzip clock output.
Power supply for ZCLK clocks, nominal 3.3V
Clock pin of I2C circuitry 5V tolerant
Power supply for PCI clocks, nominal 3.3V
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This
input is activated by the MODE selection pin / PCI clock output.
Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0 level, when input low. This
input is activated by the MODE selection pin / PCI clock output.
Asynchronous active low input pin used to power down the device into a low power state /
PCI clock output.
Ground pin for the PCI outputs
Ground pin for the 48MHz outputs
21
*(PCI_STOP#)PCICLK3
I/O
22
*(CPU_STOP#)PCICLK4
I/O
23
*(PD#)PCICLK5
I/O
24
25
GNDPCI
GND48
PWR
PWR
26
24_48MHz/SEL24_48#MHz**~
I/O
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.
27
12_48MHz/SEL12_48#MHz*
I/O
12/48MHz clock output / Latched select input for 12/48MHz output. 0=48MHz, 1 = 12MHz.
28
29
30
31
32
33
AVDD48
VDDAGP
AGPCLK1
AGPCLK0
GNDAGP
SDATA
PWR
PWR
OUT
OUT
PWR
I/O
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
Power supply for AGP clocks, nominal 3.3V
AGP clock output
AGP clock output
Ground pin for the AGP outputs
Data pin for I2C circuitry 5V tolerant
This pin establishes the reference current for the SRCCLK pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the appropriate current.
Analog Ground pin for Core PLL
3.3V Analog Power pin for Core PLL
"Complememtary" clocks of differential pair CPU outputs. These open drain outputs need
an external 1.5V pull-up.
True clock of differential pair CPU outputs. These open drain outputs need an external
1.5V pull-up.
Ground pin for the CPU outputs
True clock of differential pair CPU outputs. These open drain outputs need an external
1.5V pull-up.
Ground pin.
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Supply for SRC clocks, 3.3V nominal
Ground pin for the IOAPIC outputs.
IOAPIC clock outputs, norminal 2.5V.
IOAPIC clock outputs, norminal 2.5V.
Power pin for the IOAPIC outputs. 2.5V.
34
IREF
OUT
35
36
AGND
AVDD
PWR
PWR
37
CPUCLKODC0
OUT
38
CPUCLKODT0
OUT
39
GNDCPU
PWR
40
CPUCLKODT1
OUT
41
GND
PWR
42
SRCCLKC
OUT
43
SRCCLKT
OUT
44
45
46
47
48
VDDSRC
GNDAPIC
IOAPIC0
IOAPIC1
VDDLAPIC
PWR
PWR
OUT
OUT
PWR
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength
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