參數(shù)資料
型號(hào): ICS952607
英文描述: 16-Bit Buffers/Drivers With 3-State Outputs 48-SSOP -40 to 85
中文描述: 可編程定時(shí)控制中心,為下一代P4處理器
文件頁(yè)數(shù): 8/21頁(yè)
文件大?。?/td> 214K
代理商: ICS952607
8
Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
0734—07/16/04
I
2
C Table: Frequency Select Register
Control
Function
Frequency H/W IIC
Select
Freq Select Bit 6
Freq Select Bit 5
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
Bit 7
FS Source
RW
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FS6
FS5
FS4
FS3
FS2
FSA
FSB
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
I
2
C Table: Spreading and Device Behavior Control Register
Control
Function
Spread Select 1
Spread Select 0
Spread Enable Control
WD Soft Reset Enable
Output Control
Reserved
Output Control
Output Control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SS1
SS0
SS_EN
WDS_EN
SRC/SRC#
Reserved
CPUCLKT/C_1
CPUCLKT/C_0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
1
0
1
1
1
1
I
2
C Table: Output Control Register
Control
Function
Bit 7
SRC Stop Mode
0: SRCT Driven during
PD#; 1: Tri-stated
RW
0
Bit 6
Reserved
Reserved
RW
0
Bit 5
CPUT Stop Mode
0: CPUT Driven during
PD#; 1: Tri-stated
RW
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
3V66_2
Reserved
Reserved
Reserved
Reserved
Output Control
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
0
1
1
1
1
-
-
-
-
-
-
Disable
Enable
-
-
-
-
Driven
Hi-Z
Driven
Hi-Z
-
-
Disable
Disable
Enable
Enable
ON
OFF
Enable
Disable
01 = 0.50%
ON
11 = No Spread
OFF
-
-
27
-
-
-
Type
PWD
40,39
Byte 2
Pin #
Name
0
1
-
37,36
-
43,42
-
PWD
-
-
Byte 1
Pin #
Name
Type
00 = 0.35%
10 = 0.75%
-
-
See Table 1: QuadRom Frequency
Selection Table
0
1
PWD
-
Byte 0
Pin #
Name
Type
Latch Inputs
IIC
0
1
-
-
-
-
-
-
-
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