參數(shù)資料
型號(hào): ICS951901
英文描述: 16-Bit Buffers/Drivers With 3-State Outputs 48-TVSOP -40 to 85
中文描述: 可編程頻率發(fā)生器
文件頁(yè)數(shù): 3/19頁(yè)
文件大小: 180K
代理商: ICS951901
3
ICS951901
0670B—07/15/04
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note:
PWD = Power-Up Default
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
I
2
C is a trademark of Philips Corporation
FS3
Bit7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
Bit6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
Bit5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
Bit4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
66.67
66.67
66.67
75.00
83.31
90.00
95.00
100.00
100.00
100.00
105.00
112.00
117.99
124.09
133.34
133.34
75.00
75.00
75.00
83.31
83.32
90.00
90.00
95.00
95.00
105.00
105.00
112.00
117.99
124.09
129.99
140.00
SDRAM
MHz
66.67
100.00
133.34
75.00
83.31
90.00
95.00
66.67
100.00
133.34
105.00
112.00
117.99
124.09
100.00
133.34
100.00
112.50
150.00
111.07
166.65
60.00
120.00
63.33
126.66
70.00
140.00
84.00
88.49
93.07
97.49
105.00
PCI
MHz
33.33
33.33
33.33
37.50
33.32
30.00
31.67
33.33
33.33
33.33
35.00
33.60
35.40
31.02
33.33
33.33
37.50
32.14
32.14
33.32
31.25
30.00
30.00
31.67
31.67
35.00
35.00
33.60
35.40
31.02
32.50
35.00
AGP1
SEL=1
66.67
66.67
66.67
75.00
66.64
60.00
63.33
66.67
66.67
66.67
70.00
67.20
70.80
62.05
66.67
66.67
75.00
64.29
64.29
66.64
62.49
60.00
60.00
63.33
63.33
70.00
70.00
67.20
70.80
62.05
64.99
70.00
AGP0
SEL=0
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Spread %
PWD
Bit2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
± 0.35% center spread
Bit 2
Bit 7:4
00000
Note1
Bit 3
0 - Frequency is selected by hardware select, Latched inputs
1 - Frequency is selected by Bit, 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1 - Tristate all outputs
0
Bit 1
1
Bit 0
0
Bit
Description
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