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參數(shù)資料
| 型號： | ICS950810YFLF-T |
| 英文描述： | High-Voltage, High-Current Darlington Arrays, 18-pin DIP |
| 中文描述： | 頻率發(fā)生器200MHz的CPU的時鐘差分 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大小： | 167K |
| 代理商： | ICS950810YFLF-T |
15
ICS950810
0472F—01/12/04
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2
C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition. When the I
2
C Bit 6 of Byte 1 is programmed to '0'
the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive
current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not
be driven . When the I
2
C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU
and CPU# outputs will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#
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C
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m
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0
t
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*
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CPU_STOP#
CPUT
CPUC
CPU_STOP# - De-assertion (transition from logic "0" to logic "1")
De-assertion of CPU_STOP# Waveforms
All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the
de-assertion to active outputs is to be defined to be tetween 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit
6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 3 nS of CPU_Stop# de-assertion.
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| ICS950811AGLFT | 功能描述:IC FREQ GEN 200MHZ CLK 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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