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參數(shù)資料
| 型號(hào)： | ICS950602yGT |
| 英文描述： | Programmable Timing Control Hub for PII/III |
| 中文描述： | 可編程定時(shí)控制中心，為PII /三 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 147K |
| 代理商： | ICS950602YGT |
14
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Power Down Waveform
Note
1.
After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2
. Power-up latency <3ms.
3.
Waveform shown for 100MHz
VCO Internal
0ns
1
2
25ns
50ns
CPU 100MHz
3.3V 66MHz
PCI 33MHz
APIC 16.7MHz
PD#
SDRAM 100MHz
REF 14.318MHZ
48MHZ
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| ICS950703 | 制造商:ICS 制造商全稱:ICS 功能描述:PROGRAMMABLE TIMING CONTROL HUB FOR P4 |
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