參數(shù)資料
型號: ICS950508
英文描述: Programmable Timing Control HubTM for PII/IIITTM
中文描述: 可編程定時控制HubTM為PII / IIITTM
文件頁數(shù): 11/19頁
文件大?。?/td> 161K
代理商: ICS950508
11
Integrated
Circuit
Systems, Inc.
ICS950508
0470E—04/06/05
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Group Timing Relationship Table
1
p
u
o
r
G
z
H
M
6
6
U
P
C
z
H
M
0
0
1
M
A
R
D
S
z
H
M
0
0
1
M
A
R
D
S
S
t
s
O
e
c
n
a
T
t
s
O
e
c
n
a
T
O
M
A
R
D
S
o
U
P
C
s
n
5
s
p
0
0
5
s
n
0
s
p
0
0
5
0
6
6
V
3
o
U
P
C
s
n
5
s
p
0
0
5
s
n
0
s
p
0
0
5
0
6
6
V
3
o
M
A
R
D
S
s
n
0
s
p
0
0
5
s
n
0
s
p
0
0
5
0
z
H
M
0
0
1
U
P
C
z
H
n
p
0
p
0
p
0
0
H
M
M
0
0
a
T
5
5
5
3
3
1
1
U
A
t
s
n
s
n
s
n
P
R
C
D
s
z
c
s
s
s
M
z
H
n
p
0
p
0
p
0
0
H
M
M
3
3
a
T
5
5
5
3
3
1
1
U
A
t
n
5
n
n
5
P
R
C
D
s
O
7
0
7
5
5
0
s
A
z
c
s
s
s
M
S
e
e
0
0
s
0
0
s
s
I
C
P
o
6
6
V
3
s
n
5
s
p
0
0
5
s
n
5
s
p
0
0
5
s
n
5
s
p
0
0
5
-
s
s
c
n
n
n
s
p
0
0
5
I
T
C
O
P
D
o
C
B
S
P
s
c
n
n
0
s
A
s
n
A
0
N
s
c
n
n
0
s
A
s
n
A
0
N
s
c
n
n
0
s
A
s
n
A
0
N
s
n
A
0
N
&
U
h
y
/
h
y
/
h
y
/
h
y
/
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
SYMBOL
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input High Current
I
IH
V
IN
= V
DD
Input Low Current
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
Input Low Current
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
Operating
I
DD3.3OP
C
L
= 0 pF; Select @ 66M
Supply Current
Power Down
I
DD3.3PD
C
L
= 0 pF; With input address to Vdd or GND
Supply Current
Input frequency
F
i
V
DD
= 3.3 V;
Pin Inductance
L
pin
Input Capacitance
1
C
IN
Logic Inputs
C
out
Out put pin capacitance
C
INX
X1 & X2 pins
Transition Time
1
T
trans
To 1st crossing of target Freq.
Settling Time
1
T
s
From 1st crossing to 1% target Freq.
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq.
Delay
t
PZH
,t
PZH
output enable delay (all outputs)
t
PLZ
,t
PZH
output disable delay (all outputs)
1
Guaranteed by design, not 100% tested in production.
CONDITIONS
MIN
2
TYP
MAX
V
DD
+ 0.3
0.8
5
UNITS
V
V
mA
mA
mA
mA
V
SS
- 0.3
-5
-5
-200
100
600
mA
14.318
MHz
nH
pF
pF
pF
mS
mS
mS
nS
nS
7
5
6
27
45
3
3
3
10
10
1
1
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