參數(shù)資料
型號: ICS950220yFLF-T
英文描述: Programmable Timing Control Hub⑩ for P4⑩
中文描述: 可編程定時控制中心,為小四至⑩⑩
文件頁數(shù): 6/20頁
文件大?。?/td> 183K
代理商: ICS950220YFLF-T
6
Integrated
Circuit
Systems, Inc.
ICS950220
0467F—07/28/05
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
t
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
B
B
#
3
4
4
n
P
,
4
,
4
,
4
D
W
1
1
1
X
X
X
X
X
P
n
o
p
c
s
e
D
9
3
6
2
1
0
a
a
a
a
a
C
C
C
e
e
e
e
e
/
U
/
U
/
U
R
4
3
2
1
0
P
P
P
S
S
S
S
S
C
C
C
F
F
F
F
F
-
-
-
-
-
k
k
k
k
k
c
c
c
c
c
a
a
a
a
a
b
b
b
b
b
d
d
d
d
d
R
R
R
R
t
B
#
n
P
D
W
P
n
o
p
c
s
e
D
7
t
-
1
t
2
l
3
6
3
6
r
o
=
=
c
I
I
6
C
P
C
P
6
V
/
/
d
d
3
6
6
e
e
2
_
6
6
V
3
v
s
e
R
6
6
V
3
6
6
V
3
6
6
V
3
.
n
V
3
V
3
v
s
e
R
v
s
e
R
y
s
:
:
A
0
1
U
C
P
C
h
w
s
u
o
n
o
s
u
o
n
o
r
c
n
r
c
n
y
s
y
z
s
a
H
z
M
H
M
3
6
6
U
P
h
w
6
5
4
3
2
1
0
t
t
t
t
t
t
t
-
-
X
X
1
X
1
1
1
1
-
2
2
2
0
2
3
#
Z
H
M
8
4
_
4
d
e
3
2
1
_
_
_
1
t
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
B
B
#
n
P
D
W
X
1
1
1
1
1
1
1
P
n
o
p
c
s
e
D
-
)
c
a
b
d
a
e
R
(
L
6
_
_
_
_
_
_
_
E
K
K
K
K
K
K
K
S
L
L
L
L
L
L
L
T
L
C
I
C
I
C
I
C
I
C
I
C
I
C
I
U
C
C
C
C
C
C
C
M
P
P
P
P
P
P
P
7
6
5
2
1
0
1
1
1
1
1
1
9
5
4
3
2
1
0
Notes:
1. PWD = Power on Default
2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at
high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.
t
B
#
n
P
3
3
D
W
1
1
1
X
0
X
1
1
P
n
o
p
c
s
e
D
7
6
5
4
3
2
1
0
4
5
-
-
1
3
-
6
5
T
O
S
D
U
r
e
g
d
e
2
_
6
6
V
3
v
s
e
R
L
C
I
C
P
L
C
I
C
P
_
_
Z
z
H
H
M
M
t
s
e
R
s
e
R
8
8
4
4
B
s
e
a
s
D
=
0
,
a
n
E
=
1
t
e
d
t
v
,
Z
H
M
8
4
_
4
#
Z
H
M
8
4
_
4
2
=
0
,
H
M
6
6
6
=
1
)
a
d
(
d
8
7
e
K
K
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