參數(shù)資料
型號： ICS94236YF-T
英文描述： Programmable System Clock Chip for AMD - K7⑩ processor
中文描述： 可編程系統(tǒng)時(shí)鐘芯片為AMD - k7的⑩處理器
文件頁數(shù)： 6/17頁
文件大?。?/td> 226K
代理商： ICS94236YF-T
6
ICS94236
0451A
—
01/10/03
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
7
t
B
-
X
6
t
B
6
4
1
5
t
B
-
1
4
t
B
-
X
3
t
B
0
4
1
2
t
B
-
X
N
O
I
T
P
I
R
C
S
E
D
#
2
U
v
R
(
3
S
F
R
D
S
L
E
S
U
P
C
e
m
o
C
v
R
(
S
P
F
C
K
)
e
L
C
#
T
U
O
#
8
4
_
0
K
L
C
l
e
m
i
*
e
_
M
4
A
2
1
t
B
4
4
4
1
h
"
b
u
"
e
a
.
p
y
n
e
d
n
a
)
0
t
B
-
1
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
7
6
5
4
3
2
1
0
I
B
B
B
B
B
B
B
B
B
#
N
-
7
-
3
1
2
1
1
0
1
8
I
P
D
W
X
1
1
1
1
1
1
1
P
N
O
I
T
P
I
R
C
S
E
D
t
t
t
t
t
t
t
t
#
C
0
I
S
C
v
R
C
I
C
P
I
C
P
I
C
P
I
C
P
I
C
P
F
P
(
F
_
)
e
4
K
L
K
L
K
L
K
L
K
L
K
L
3
2
1
0
C
C
C
C
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
7
6
5
4
3
2
1
0
I
B
B
B
B
B
B
B
B
B
#
N
8
2
9
2
1
3
2
3
4
3
5
3
7
3
8
3
I
P
D
W
1
1
1
1
1
1
1
1
P
N
O
I
T
P
I
R
C
S
E
7
6
5
4
3
2
1
0
D
t
t
t
t
t
t
t
t
M
M
M
M
M
M
M
M
A
A
A
A
A
A
A
A
R
R
R
R
R
R
R
R
D
D
D
D
D
D
D
D
S
S
S
S
S
S
S
S
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
T
7
6
5
4
3
2
1
0
I
B
B
B
B
B
B
B
B
B
#
N
-
-
-
-
-
-
8
4
2
I
P
D
W
1
1
1
X
X
1
1
1
P
N
O
I
T
P
I
R
C
S
E
D
)
e
)
e
)
e
t
t
t
t
t
t
t
t
v
R
(
v
R
(
v
R
(
d
o
M
1
S
F
v
R
(
F
E
R
F
E
R
e
#
)
e
1
0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
B
B
B
B
B
B
B
B
#
N
-
-
-
-
-
-
-
-
I
P
D
W
0
0
0
0
0
1
1
0
P
N
O
I
T
P
I
R
C
)
N
)
N
)
N
)
N
)
N
)
N
)
N
)
N
S
(
(
(
(
(
(
(
(
E
d
d
d
d
d
d
d
d
D
e
e
e
e
e
e
e
e
7
6
5
4
3
2
1
0
v
R
v
R
v
R
v
R
v
R
v
R
v
R
v
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don
’
t write into this register, writing into this
register can cause malfunction
T
7
6
5
4
3
2
1
0
I
B
B
B
B
B
B
B
B
B
#
N
-
-
6
2
5
2
7
1
8
1
0
2
1
2
I
P
D
W
1
1
1
1
1
1
1
1
P
N
O
I
T
P
I
R
C
S
E
D
)
e
)
e
z
H
M
M
A
M
A
M
A
M
A
t
t
t
t
t
t
t
t
v
R
(
v
R
(
M
8
4
4
_
4
2
R
D
S
R
D
S
R
D
S
R
D
S
H
8
z
1
0
1
1
9
8
Note:
* It is recommended to drive this bit to 0.
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