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參數(shù)資料
| 型號： | ICS94206yF-T |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:10; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:12-98 |
| 中文描述： | 可編程系統(tǒng)頻率發(fā)生器有價證券/三⑩ |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 189K |
| 代理商： | ICS94206YF-T |
15
ICS94206
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the
ICS94206
. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU
clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state
and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and
CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS94206.
3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the
ICS94206
CLK_STOP# signal. SDRAM's are controlled as shown.
5. All other clocks continue to run undisturbed.
PCICLK
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
IOAPIC
PCI_STOP# (High)
CLK_STOP#
INTERNAL
CPUCLK
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