參數(shù)資料
型號： ICS94203
英文描述： 18-Bit Universal Bus Transceivers With 3-State Outputs 56-SSOP -40 to 85
中文描述： 可編程系統(tǒng)頻率發(fā)生器有價證券/三⑩
文件頁數(shù)： 6/18頁
文件大?。?/td> 183K
代理商： ICS94203
6
ICS94203
2. PWD = Power on Default
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Byte 5: Output Control Register
(1 = enable, 0 = disable)
Byte 6: Byte Count Read Back Register
Note: Writing to this register will configure byte count and
how many bytes will be read back, default is 6 bytes.
t
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
B
#
n
3
3
4
4
4
4
4
4
D
W
1
1
1
1
1
1
1
1
P
n
o
D
7
M
6
M
5
M
4
M
3
M
2
M
1
M
0
M
7
6
5
4
3
2
1
0
8
9
0
1
4
5
6
7
A
A
A
A
A
A
A
A
R
R
R
R
R
R
R
R
D
D
D
D
D
D
D
D
S
S
S
S
S
S
S
S
t
t
B
t
B
t
B
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B
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B
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B
t
B
t
B
B
#
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D
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1
1
1
1
1
X
1
1
P
n
o
D
7
6
5
4
3
2
1
0
9
7
8
6
5
4
5
-
0
5
5
2
0
1
_
_
_
6
6
6
6
6
6
F
A
V
V
V
E
O
v
R
U
P
C
U
P
C
3
3
3
R
I
0
d
K
K
C
e
L
L
I
1
0
C
C
1
t
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
B
#
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D
W
0
0
0
0
0
1
1
0
P
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N
(
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N
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N
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d
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7
6
5
4
3
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1
0
-
-
-
-
-
-
-
-
v
R
v
R
v
R
v
R
v
R
v
R
v
R
v
R
t
t
B
t
B
t
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t
B
t
B
t
B
t
B
t
B
B
#
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D
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1
1
1
1
1
1
1
1
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1
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D
S
1
M
A
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D
S
9
M
A
R
D
S
8
M
A
R
D
S
7
6
5
4
3
2
1
0
-
-
-
-
(
(
(
(
1
2
3
4
3
3
3
3
1
0
t
t
B
t
B
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B
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B
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B
t
B
t
B
B
#
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D
W
0
1
1
1
1
1
1
1
P
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o
D
d
6
K
5
K
4
K
3
K
2
K
1
K
0
K
7
6
5
4
3
2
1
0
-
0
9
1
1
1
4
1
1
2
1
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R
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C
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I
C
P
I
C
P
I
C
P
I
C
P
I
C
P
I
C
P
2
L
L
L
L
L
L
L
C
C
C
C
C
C
C
8
7
3
t
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
B
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1
1
1
1
1
1
1
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M
A
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D
S
7
6
5
4
3
2
1
0
-
-
-
v
R
(
v
R
(
v
R
(
4
_
4
2
v
R
(
8
4
7
-
8
2
-
3
2
8
7
F
_
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