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參數(shù)資料
| 型號： | ICS94201yFT |
| 英文描述： | Programmable System Frequency Generator for PII/III⑩ |
| 中文描述： | 可編程系統(tǒng)頻率發(fā)生器有價(jià)證券/三⑩ |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 357K |
| 代理商： | ICS94201YFT |
11
ICS94201
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Group Timing Relationship Table
1
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input High Current
I
IH
V
IN
= V
DD
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
C
L
= max cap loads;
CPU=66-133 MHz, SDRAM=100 MHz
CPU=133 MHz, SDRAM=133 MHz
I
DD2.5OP
C
L
= max cap loads;
Powerdown Current
I
DD3.3PD
C
L
= 0 pF; Input address to VDD or GND
Input Frequency
F
i
V
DD
= 3.3 V
Pin Inductance
L
pin
C
IN
Logic Inputs
C
OUT
Output pin capacitance
C
INX
X1 & X2 pins
Transition time
1
T
trans
To 1st crossing of target frequency
Settling time
1
T
s
From 1st crossing to 1% target frequency
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target frequency
t
PZH
,t
PZL
Output enable delay (all outputs)
t
PHZ
,t
PLZ
Output disable delay (all outputs)
MIN
2
TYP
MAX
V
DD
+0.3
0.8
UNITS
V
V
μ
A
V
SS
-0.3
-5
-5
5
-200
334
350
465
20
280
14.318
500
70
600
μ
A
MHz
nH
pF
pF
pF
ms
ms
ms
ns
ns
7
5
6
27
45
3
3
3
10
10
1
1
1
Guaranteed by design, not 100% tested in production.
Delay
1
Input Capacitance
1
Input Low Current
μ
A
I
DD3.3OP
Operating Supply
Current
mA
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
CPU to SDRAM
2.5 ns
500 ps
5.0 ns
500 ps
0.0 ns
500 ps
3.75 ns
500 ps
CPU to 3V66
7.5 ns
500 ps
5.0 ns
500 ps
0.0 ns
500 ps
0.0 ns
500 ps
SDRAM to 3V66
0.0 ns
500 ps
0.0 ns
500 ps
0.0 ns
500 ps
3.75 ns
500 ps
3V66 to PCI
1.5-3.5ns
500 ps
1.5-3.5ns
500 ps
1.5-3.5ns
500 ps
1.5-3.5ns
500 ps
PCI to IOAPIC
0.0 ns
1.0 ns
0.0 ns
1.0 ns
0.0 ns
1.0 ns
0.0 ns
1.0 ns
USB & DOT
Asynch
N/A
Asynch
N/A
Asynch
N/A
Asynch
N/A
1
Guaranteed by design, not 100% tested in production.
Group
SDRAM 100 MHz
SDRAM 100 MHz
SDRAM 100 MHz
SDRAM 133 MHz
CPU 66 MHz
CPU 100 MHz
CPU 133 MHz
CPU 133 MHz
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