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參數(shù)資料
| 型號： | ICS93705 |
| 英文描述： | DDR Phase Lock Loop Zero Delay Clock Buffer |
| 中文描述： | 復員鎖相環(huán)零延遲時鐘緩沖器 |
| 文件頁數(shù)： | 7/7頁 |
| 文件大?。?/td> | 65K |
| 代理商： | ICS93705 |
7
ICS93705
0418C—08/08 /02
Ordering Information
ICS93705
y
F-T
Example:
ICS XXXX
y
F PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
F=SSOP
Revision Designator
(will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
MIN
2.413
0.203
0.203
0.127
SEE VARIATIONS
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
SEE VARIATIONS
MAX
.110
.016
.0135
.010
A
A1
b
c
D
E
E1
e
h
L
N
10.033
7.391
10.668
7.595
.395
.291
.420
.299
0.635 BASIC
0.381
0.508
SEE VARIATIONS
0.025 BASIC
.015
.020
SEE VARIATIONS
0.635
1.016
.025
.040
α
0°
8°
0°
8°
VARIATIONS
MIN
MAX
16.002
MIN
MAX
48
15.748
.620
.630
6/1/00
REV B
JEDEC MO-118
DOC# 10-0034
N
D mm.
D (inch)
SYMBOL
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
AREA
INDEX
1 2
N
D
h x 45°
E1
E
α
PLANE
SEATING
A1
A
e
- C -
b
.10 (.004) C
c
L
300 mil SSOP
相關PDF資料 |
PDF描述 |
|---|---|
| ICS93705YF-T | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712YF-PPP-T | 2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 2 DIMM DDR Fanout Buffer |
| ICS93712 | 2 DIMM DDR Fanout Buffer |
| ICS93716 | Low Cost DDR Phase Lock Loop Clock Driver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS93705YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712 | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-PPP-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93716 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Cost DDR Phase Lock Loop Clock Driver |
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