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參數(shù)資料
| 型號： | ICS9341YF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 207K |
| 代理商： | ICS9341YF |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9341
Block Diagram
133MHz Clock Generator and Integrated Buffer for PowerPC
9341 Rev A 10/12/99
Pin Configuration
48-pin SSOP
* Internal pull-up resistor of 120K to 3.3V on
indicated inputs
** Internal pull-down resistor of 120K to GND
on indicated inputs.
Generates the following system clocks:
- 4-CPUA(3.3V, up to 133MHz)
- 4-CPUB (3.3V, up to 133MHz)
- 8-PCI(3.3V,33.3MHz)
- 1-OUT(3.3v,64MHz)
- 1-OUT/2(3.3V,OUT/2MHz)
- 2-REF(3.3V,14.318MHz)
Up to 133MHz frequency support.
Stop clocks for power management
Spread Spectrum for EMI control
±.25% center spread
Skew characteristics:
- CPU - CPU: <350ps
- CPU - PCI: <500ps
- PCI - PCI: <500ps
The ICS9341 generates all clocks required for high speed
PowerPC RISC microprocessor systems. Generating clocks in
phase with an external reference frequency.
Spread Spectrum may be enabled by driving the SS_EN pin
active. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9341
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Power Groups:
VDDREF,GNDREF=REF,X1,X2
GNDPCI,VDDPCI=PCICLK
VDD66,GND66=3V66
VDD48,GND48=48MHz
VDDCOR,GNDCOR=PLLCore
VDDLCPU/2,GNDLCPU/2=CPU/2
VDDLIOAPIC,GNDIOAPIC=IOAPIC
PD#
CPUB_STOP#
OUT_SEL (0:1)
PCI_STOP#
SS_EN
X1
X2
OSC
PLL
Spread
Spectrum
REF (0:1)
2
4
OUT
OUT/2
CPUCLKB (1:4)
CPUCLKA (1:4)
STOP
C
o
n
t
r
o
l
/ 2
PLL2
8
PCICLK (1:8)
STOP
/ 8
/ 6
/ 5
/ 4
/ 2
/ 4
/ 5
/ 6
/ 3
GNDREF
X1
X2
VDDPCI
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GNDPCI
GNDCPUB
CPUB1
CPUB2
CPUB3
CPUB4
VDDCPUB
VDDPCI
PCICLK5
PCICLK6
PCICLK7
PCICLK8
FS0
FS1
*OUT_SEL0
GNDPCI
REF1
REF0
VDDREF
CPUA1
CPUA2
SS_EN
GNDCPUA
OUT_SEL1*
PD#
VDDCPUA
CPUA3
CPUA4
CPUB_STOP#**
VDDD
VDDOUT
OUT
OUT/2
GNDOUT
GNDA
GNDD
N/C
*PCI_STOP#
VDDA
ICS9341
1
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4
5
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9
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16
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20
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48
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45
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ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9342 | 制造商:ICS 制造商全稱:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS9342AFLF | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS9342YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS93701 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93701YGT | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
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