參數資料
型號: ICS9248yF-80-T
英文描述: General Purpose 133MHz System Clock
中文描述: 通用133MHz的系統時鐘
文件頁數: 7/11頁
文件大?。?/td> 100K
代理商: ICS9248YF-80-T
7
ICS9248-185
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the
ICS9248-185
. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-185.
3. All other clocks continue to run undisturbed.
PCICLK
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
PCI_STOP# (High)
CLK_STOP#
INTERNAL
CPUCLK
相關PDF資料
PDF描述
ICS9248-151 18-Bit Bus-Interface Flip-Flops With 3-State Outputs 56-SSOP -40 to 85
ICS9248-153 18-Bit Bus-Interface Flip-Flops With 3-State Outputs 56-SSOP -40 to 85
ICS9248-157 18-Bit Bus-Interface Flip-Flops With 3-State Outputs 56-SSOP -40 to 85
ICS9248-162 Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6
ICS9248-168 18-Bit Buffers/Drivers With 3-State Outputs 56-SSOP -40 to 85
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