參數(shù)資料
型號(hào): ICS9248yF-64
英文描述: AMD-K7TM System Clock Chip
中文描述: AMD的K7TM系統(tǒng)時(shí)鐘芯片
文件頁數(shù): 8/11頁
文件大?。?/td> 100K
代理商: ICS9248YF-64
8
ICS9248-185
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the
ICS9248-185
. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the
ICS9248-185
internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCICLK [6:0]
PCI_STOP#
相關(guān)PDF資料
PDF描述
ICS9248yF-65 Frequency Timing Generator for PENDIUM II Systems
ICS9248yF-66 Frequency Timing Generator for PENTIUM II Systems
ICS9248yF-80-T General Purpose 133MHz System Clock
ICS9248-151 18-Bit Bus-Interface Flip-Flops With 3-State Outputs 56-SSOP -40 to 85
ICS9248-153 18-Bit Bus-Interface Flip-Flops With 3-State Outputs 56-SSOP -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS9248YF-65 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENDIUM II Systems
ICS9248YF-66 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems
ICS9248YF-72 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems
ICS9248YF-73-T 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems
ICS9248YF-77 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems