- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67112 > ICS9248YF-24LF PLL BASED CLOCK DRIVER, 22 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO56 PDF資料下載
參數(shù)資料
| 型號： | ICS9248YF-24LF |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 22 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO56 |
| 封裝： | 0.300 INCH, SSOP-56 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 83K |
| 代理商： | ICS9248YF-24LF |
Integrated
Circuit
Systems, Inc.
ICS9250-24
0390C—11/06/02
Pin Configuration
Recommended Application:
General purpose peripheral clk gen, also for IA64.
Output Features:
12 - PCI clocks @ 3V
2 - 48MHz clocks
6 - 3V66 66MHz reference output
2 - 14.318 reference output
Features:
Effective power management scheme through PD#
14.318MHz reference input
66MHz reference input
Key Specifications:
48MHz Output Jitter: <350ps
3V66 to PCI Skew: 1.5 to 3.5ns
PCI to PCI Skew: <500ps
3V66 to 3V66 Skew: <250ps
Integrated Buffers for PIII
Functionality
56-Pin 300mil SSOP & TSSOP
0
S
F1
S
F2
S
Fn
o
i
t
p
i
r
c
s
e
Ds
l
i
a
t
e
D
00
0
n
o
s
t
u
p
t
u
o
ll
An
o
s
t
u
p
t
u
o
ll
A
00
1
f
o
)
0
:
7
(
I
C
P
,
1
,
4
1
,
5
1
,
7
1
,
8
1
s
n
i
P
W
O
L
d
l
e
h
6
,
7
,
0
1
01
0
f
o
)
0
:
5
(
I
C
P
6
,
7
,
0
1
,
1
,
4
1
,
5
1
s
n
i
P
W
O
L
d
l
e
h
01
1
f
o
I
C
P
ll
AW
O
L
d
l
e
h
s
t
u
p
t
u
o
I
C
P
ll
A
10
0
e
t
a
t
s
i
r
T
h
g
i
h
s
t
u
p
t
u
o
ll
A
e
c
n
a
d
e
p
m
i
10
1
f
o
5
-
6
V
3W
O
L
d
l
e
h
1
5
n
i
P
11
0
f
o
)
0
:
1
(
F
E
RW
O
L
d
l
e
h
4
5
,
5
s
n
i
P
11
1
f
o
1
-
z
H
M
8
4W
O
L
d
l
e
h
7
3
n
i
P
SDATA
SCLK
FS (2:0)
PD#
PLL
48MHz (1:0)
2
REF (1:0)
14.318_IN
Control
Logic
Config.
Reg.
12
6
3V66 (5:0)
PCICLK (11:0)
66_IN
/ 2
Delay
GND
14.318_IN
VDD
66_IN
GND
PCICLK0
PCICLK1
VDD
GND
PCICLK2
PCICLK3
VDD
GND
PCICLK4
PCICLK5
VDD
PCICLK6
PCICLK7
GND
VDD
PCICLK8
PCICLK9
GND
PCICLK10
PCICLK11
VDD
FS0
FS1
VDD
REF-1
REF-0
GND
VDD
3V66-5
3V66-4
GND
3V66-3
3V66-2
VDD
3V66-1
3V66-0
GND
VDD
GND
AVDD
48MHz-1
48MHz-0
AGND
FS2
PD#
VDD
GND
SCLK
SDATA
ICS9250-24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Block Diagram
Power Groups
AGND = Analog ground
AVDD = Analog power
相關PDF資料 |
PDF描述 |
|---|---|
| ICS9248YF-24 | PLL BASED CLOCK DRIVER, 22 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO56 |
| ICS9248YF-24LF | PLL BASED CLOCK DRIVER, 22 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO56 |
| ICS9342YF-PPP-T-LF | 146.62 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9342YF-PPP-T | 146.62 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS93712YF-T | LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9248YF-39 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9248YF-64 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD-K7TM System Clock Chip |
| ICS9248YF-65 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENDIUM II Systems |
| ICS9248YF-66 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248YF-72 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
發(fā)布緊急采購，3分鐘左右您將得到回復。