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參數(shù)資料
| 型號(hào)： | ICS9248-171 |
| 英文描述： | AMD - K7TM System Clock Chip |
| 中文描述： | AMD公司- K7TM系統(tǒng)時(shí)鐘芯片 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 210K |
| 代理商： | ICS9248-171 |
2
ICS9248-171
Advance Information
Third party brands and names are the property of their respective owners.
Pin Descriptions
PIN NUMBER
Notes:
1:
2:
3:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
Internal pull-down resistor of 120K to GND.
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
PIN NAME
TYPE
DESCRIPTION
1
DG_STOP#
1
IN
DG_STOP halts SDRAM and/or AGP clocks at logic "0" when driven low.
The stops selection can be programed through I
2
C.
2
PD#
1
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
4
5
X1
X2
IN
OUT
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
3, 11, 16, 23, 29,
34, 41, 48
8, 17, 28, 35, 40
6
GND
PWR
Ground pins
VDD
AVDD
FS0
2, 3
REF0
FS1
2, 3
AGP0
AGP1
PCICLK_F
FS2
1, 3
PCICLK
(5:4) (2:0)
PCICLK3
MODE
1, 3
AVDD48
FS3
2, 3
48MHz
SCLK
PWR
PWR
IN
OUT
IN
OUT
OUT
OUT
IN
Power supply pins, nominal 3.3V
Analog power supply pin, nominal 3.3V
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
AGP outputs defined as 2X PCI. These may not be stopped.
AGP outputs defined as 2X PCI. These may not be stopped.
Free running PCICLK not stoped by PCI_STOP#
Frequency select pin.
10
20, 19, 15, 14, 13
OUT
PCI clock outputs.
OUT
IN
PWR
IN
OUT
IN
PCI clock output.
Function select pin, 1=Desktop Mode, 0=Mobile Mode.
Analog power supply pin, nominal 3.3V
Frequency select pin.
48MHz output clock
Clock input of I
2
C input, 5V tolerant input
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
SDRAM clock output.
21
24
PCI_STOP#
1
IN
SDRAM10
OUT
25, 26, 30, 31, 32,
33, 36, 37, 38, 39,
42, 43
44
SDRAM
(12:11, 9:0 )
OUT
SDRAM clock outputs.
SDATA
I/O
Data pin for I
2
C circuitry 5V tolerant
"True" clocks of differential pair CPU outputs. These open drain outputs
need an external 1.5V pull-up.
"Complementory" clocks of differential pair CPU outputs. This open drain
output need an external 1.5V pull-up.
45, 47
CPUCLKT (1:0)
OUT
46
CPUCLKC0
OUT
9
7
27
12
22
18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS9248YF-171-T | AMD - K7TM System Clock Chip |
| ICS9248YG-171-T | AMD - K7TM System Clock Chip |
| ICS9248-185 | Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6 |
| ICS9248-131 | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248yF-131-T | Pleated Foil Flat Jacketed Cable, 93101/68 30 AWG, .025 (0.64) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9248-185 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6 |
| ICS9248-189 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K7⑩ Clock Generator for Mobile System |
| ICS9248-192 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Transmeta Systems |
| ICS9248-195 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM II/III & K6 |
| ICS9248-199 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator for SIS 735/740 with AMD K7 Processor |
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