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參數(shù)資料
| 型號： | ICS9178-03 |
| 英文描述： | 245 MHz Clock Generator and Integrated Buffer for PowerPC™ |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 526K |
| 代理商： | ICS9178-03 |
6
ICS9178-03
AC Characteristics (continued)
V
DD
=+5V ±5%, 0°C
≥
TAMBIENT
≥
+70°C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production.
Note 2: For 70
Load, 2XPCLK level may be pulled-up with a 390
resistor to meet minimum pulse width requirements
at both 1.8Vand 0.6Vat 240 Mhz.
Note 3: 2XPCLK is normally earlier than DCLK by up to 600ps and can be later by up to
PARAMETER
SYMBOL
TEST CONDITIONS
for 200 to 240 MHz on
2XPCLK at VDD 4.9 to
5.2V
for 200 to 240 MHz on
2XPCLK at VDD 4.9 to
5.2V
for < 200 MHz on 2XPCLK
for < 200 MHz on 2XPCLK
for < 200 MHz on 2XPCLK
MIN
TYP
MAX
UNITS
Jitter Absolute 2XPCLK (Note 1)
T
jabs4
-125
80
+125
ps
Jitter Absolute 1XPCLK, B, D clocks
(Note 1)
T
jabs5
-160
110
+160
ps
Jitter Absolute 2XPCLK (Note 1)
Jitter Absolute 1XPCLK (Note 1)
Jitter Absolute AB clock (Note 1)
Skew, output to output (P, B, D , AB abd
XCLKs) (Note 1)
Skew, 2XPCLK to PCLK (2XPCLK is
earlier than PCLK) (Note 1)
Skew, 2XPCLK to REFCLK (2XPCLK is
earlier) (Note 1)
Skew, 2XPCLK to DCLK (Notes 1,3)
T
jabs6
T
jabs7
T
jabs8
-200
-250
-300
-
-
-
+200
+250
+300
ps
ps
ps
T
skew1
@ 1.4V
-250
-
+250
ps
T
skew2
@ 1.4V
-600
-300
0
ps
T
skew3
for 240 MHz on 2XPCLK
@ 1.4V
@ 1.4V
-600
-300
0
ps
T
skew4
-600
-100
100
ps
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9178Y-03 | 制造商:ICS 制造商全稱:ICS 功能描述:245 MHz Clock Generator and Integrated Buffer for PowerPC™ |
| ICS9179-03 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Skew Fan Out Buffers |
| ICS9179-06 | 制造商:ICS 制造商全稱:ICS 功能描述:Zero Delay Buffers |
| ICS9179-12 | 制造商:ICS 制造商全稱:ICS 功能描述:3 DIMM Buffer |
| ICS9179B-01 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Skew Buffers |
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