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參數(shù)資料
| 型號： | ICS91309MLF-T |
| 英文描述： | High performance Communication Buffer |
| 中文描述： | 高性能通信緩沖區(qū) |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 106K |
| 代理商： | ICS91309MLF-T |
6
ICS91309
0093G—02/11/04
Application Suggestion:
ICS91309
is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise
generated by charging or discharging of internal or external capacitor on the power supply pins. This type of noise will
cause excess jitter to the outputs of
ICS91309
. Below is a recommended lay out to alleviate any addition noise. For
additional information on FT. layout, please refer to our AN07. The 0.1 uF capacitors should be connected as close as
possible to power pins (4 & 13). An Isolated power plane with a 2.2 uF capacitor to ground will enhance the power line
stability.
33
33
33
33
10K
0.1μF
VDD
GND
33
33
33
33
33
10K
0.1μF
VDD
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
FS2
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
FS1
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