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參數(shù)資料
| 型號(hào)： | ICS9112YM-28-T |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, MS-012, SOIC-8 |
| 文件頁(yè)數(shù)： | 1/3頁(yè) |
| 文件大?。?/td> | 74K |
| 代理商： | ICS9112YM-28-T |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9112-28
Preliminary Product Preview
Block Diagram
Low Skew Output Buffer
9112-28 Rev A 02/13/02
Pin Configuration
Frequency range 0 - 133 MHz (3.3V)
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC &
173 mil TSSOP packages.
3.3V ±10% operation
The ICS9112-28 is a high performance, low skew, low jitter
clock driver. It is designed to distribute high speed clocks in
PC systems operating at speeds from 0 to 133 MHz.
The ICS9112-28 comes in an eight pin 150 mil SOIC package.
It has four output clocks.
8 pin SOIC
CLK_IN
CLK0
GND
CLK1
CLK4
VDD
CLK3
CLK2
ICS9112-28
1
2
3
4
8
7
6
5
CLK_IN
CLK0
CLK1
CLK2
CLK3
CLK4
Pin Descriptions
Notes:
1.
Weak pull-down on all outputs
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PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
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