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87972DYI
www.idt.com
REV. E JUNE 25, 2010
12
ICS87972I
LOW SKEW, 1-TO-12
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
APPLICATION SCHEMATIC EXAMPLE
Figure 4 shows an application schematic example of
ICS87972I. This example provides general handling of input/
output termination, logic control input and power supply filter-
ing. In this example, the clock inputs are driven by LVCMOS
drivers. Series termination for LVCMOS drivers is shown. Ad-
ditional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. The logic control in-
R11
33
R2
43
Zo = 50
R10
33
RD2
1K
(U1-17)
(U1-33)
VDD
R9
33
VDD=3.3V
R5
1K
RD1
Not Install
RU1
1K
C7
0.1uF
R2
43
R1
43
(U1-37)
Zo = 50
Logic Input Pin Examples
U1
87972i
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
39
38
37
36
35
34
33
32
31
30
29
28
27
52
51
50
49
48
47
46
45
44
43
42
41
40
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2
PLL_SEL
REF_SEL
CLK_SEL
CLK0
CLK1
XTAL1
XTAL2
VDDA
IN
V
_
C
L
K
G
NDO
QC
3
V
DDO
QC
2
F
SEL_
C
1
F
SEL_
C
0
QC
1
V
DDO
QC
0
G
NDO
QSYN
C
F
SEL_
F
B1
GNDO
QB0
VDDO
QB1
GNDO
QB2
VDDO
QB3
EXT_FB
GNDO
QFB
VDD
FSEL_FB0
VC
O_SE
L
G
NDO
QA
0
V
DDO
QA
1
G
NDO
QA
2
V
DDO
QA
3
F
S
E
L_A
0
F
S
E
L_A
1
F
S
E
L_B
0
F
S
E
L_B
1
Zo = 50
C6
0.1uF
Ro=16 Ohm
LVCMOS
(U1-45)
VDD
Zo = 50
To Logic
Input
pins
R12
33
LVCMOS
Ro=16 Ohm
LVCMOS
R8
1K
Set Logic
Input to
'0'
VDD
C11
0.01u
VDDO=3.3V
LVCMOS
Zo = 50
R13
1K
R3
43
C8
0.1uF
R14
1K
R7
10 - 15
Zo = 50
VDD
C3
0.1uF
C4
0.1uF
(U1-49)
C5
0.1uF
To Logic
Input
pins
Ro=16 Ohm
LVCMOS
RU2
Not Install
VDDO
Ro=16 Ohm
LVCMOS
VDDO
(U1-22)
VDD
Zo = 50
VDD
Set Logic
Input to
'1'
C16
10u
C9
0.1uF
put can be either hardwired on the board or controlled by
LVCMOS drivers. In this example, both hardwired and
LVCMOS driver controlling the logic input are shown. For the
power supply pins, it is recommended at least one decoupling
capacitor per power pin. The decoupling capacitors should
be placed as close to the power pins as possible.
FIGURE 4. ICS87972I LAYOUT SCHEMATIC