- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9007 > ICS87951AYI-147LFT (IDT, Integrated Device Technology Inc)IC BUFFER ZD 1-9 LOW SKEW 32LQFP PDF資料下載
參數(shù)資料
| 型號： | ICS87951AYI-147LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER ZD 1-9 LOW SKEW 32LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | HiPerClockS™ |
| 類型： | 零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | HCSL，LVCMOS，LVDS，LVHSTL，LVPECL，LVTTL，SSTL |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:9 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 250MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 87951AYI-147LFT |
BelaSigna 300
http://onsemi.com
10
The DGND plane is used as the ground return for digital
circuits and should be placed under digital circuits. The
AGND plane should be kept as noisefree as possible. It is
used as the ground return for analog circuits and it should
surround analog components and pins. It should not be
connected to or placed under any noisy circuits such as RF
chips, switching supplies or digital pads of BelaSigna 300
itself. Analog ground returns associated with the audio
output stage should connect back to the star point on separate
individual traces.
For details on which signals require special design
In some designs, space constraints may make separate
ground planes impractical. In this case a star configuration
strategy should be used. Each analog ground return should
connect to the star point with separate traces.
Internal Power Supplies
Power management circuitry in BelaSigna 300 generates
separate digital (VDDC) and analog (VREG, VDBL)
regulated supplies. Each supply requires an external
decoupling capacitor, even if the supply is not used
externally. Decoupling capacitors should be placed as close
as possible to the power pads. The VDDC internal regulator
is a programmable power supply that allows the selection of
the lowest digital supply depending on the clock frequency
at which BelaSigna 300 will operate. See the Internal Digital
Supply Voltage section for more details on VDDC.
Two other supply pins are also available on BelaSigna 300
(VDDO and VDDO_SPI). On the WLCSP option, these two
pins are internally connected to the VBAT pin, whereas the
DFN package option considers these two pins as inputs. In
this case, they must be externally connected by the
application PCB.
Further details on these critical signals are provided in
Table 9. CRITICAL SIGNALS
Pin Name
Description
Routing Guideline
VBAT
Power supply
Place 1 mF (min) decoupling capacitor close to pin.
Connect negative terminal of capacitor to DGND plane.
VREG, VDBL
Internal regulator for
analog sections
Place separate 1 mF decoupling capacitors close to each pin.
Connect negative capacitor terminal to AGND.
Keep away from digital traces and output traces.
VREG may be used to generate microphone bias.
VDBL shall not be used to supply external circuitry.
AGND
Analog ground return
Connect to AGND plane.
VDDC
Internal regulator for digital core
Place 10 mF decoupling capacitor close to pin.
Connect negative terminal of capacitor to DGND.
GNDC
Digital ground return
Connect to digital ground.
VDDO
Digital I/O power
Connect to VDDC, unless the pad ring must use different voltage levels
Not available on WLCSP option (routed internally to VBAT)
VDDO_SPI
Supply for SPI interface I/O
Connect to VDDC, unless the SPI port must use different voltage levels
Not available on WLCSP option (routed internally to VBAT)
GNDO
Digital ground return
Connect to digital ground.
Not available on WLCSP option (routed internally to GNDC)
AI0/LOUT0,
AI1/LOUT1,
AI2/LOUT2,
AI3/LOUT3, AI4
Audio inputs
Keep as short as possible.
Keep away from all digital traces and audio outputs.
Avoid routing in parallel with other traces.
Connect unused inputs to AGND.
AI3/LOUT3 not available on WLCSP option
RCVR+, RCVR,
RCVR_HP+,
RCVR_HP
Direct digital audio output
Keep away from analog traces, particularly audio inputs.
Corresponding traces should be of approximately the same length.
Ideally, route lines parallel to each other.
GNDRCVR
Output stage ground return
Connect to star point.
Keep away from all analog audio inputs.
EXT_CLK
External clock input / internal
clock output
Minimize trace length. Keep away from analog signals. If possible, sur-
round with digital ground.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS271PGILFT | VCXO CLK TRPL PLL PROGR 20-TSSOP |
| SL28PCIE30ALIT | IC CLOCK PCIE GEN2 DIFF 32QFN |
| VE-B0T-MY-F2 | CONVERTER MOD DC/DC 6.5V 50W |
| ICS291PGLF | IC CLK SYNTH TRPL PLL 20-TSSOP |
| VE-2NW-MW-F1 | CONVERTER MOD DC/DC 5.5V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS87951AYILF | 功能描述:IC CLK ZDB 1:9 180MHZ 32LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS87951AYILFT | 功能描述:IC CLK ZDB 1:9 180MHZ 32LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS87952AYI-147LF | 功能描述:IC CLK MULT/ZD BUFFER 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS87952AYI-147LFT | 功能描述:IC CLK MULT/ZD BUFFER 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS87972DYI-147LF | 功能描述:IC CLK MULT/ZD BUFFER 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。