參數(shù)資料
型號: ICS8741004
廠商: Integrated Device Technology, Inc.
英文描述: DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS⑩ JITTER ATTENUATOR
中文描述: DIFFERENTIAL-TO-LVDS/0.7V微分的PCI Express⑩抖動衰減器
文件頁數(shù): 3/17頁
文件大?。?/td> 715K
代理商: ICS8741004
ICS8741004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR
IDT / ICS
PCI EXPRESS JITTER ATTENUATOR
3
ICS8741004AG REV. AAUGUST 3, 2007
Table 1. Pin Descriptions
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Number
Name
Type
Description
1, 24
QA1, QA1
Output
Differential output pair. LVDS interface levels.
3, 22
V
DDO
Power
Output supply pins.
4, 5
QA0, QA0
Output
Differential output pair. LVDS interface levels.
6
MR
Input
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q[Ax:Bx] to go LOW and the inverted outputs
Q[Ax:Bx] to go HIGH. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
7
BW_SEL
Input
Pullup/
Pulldown
PLL Bandwidth input. LVCMOS/LVTTL interface levels. See Table 3B.
8
nc
Unused
No connect.
9
V
DDA
Power
Analog supply pin.
10
F_SELA
Input
Pulldown
Frequency select pins for QAx/QAx outputs.
LVCMOS/LVTTL interface levels. See Table 3C.
11
V
DD
Power
Core supply pin.
12
OEA
Input
Pullup
Output enable for QAx pins. When HIGH, QAx/QAx outputs are enabled.
When LOW, the QAx/QAx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels. See Table 3A.
13
CLK
Input
Pulldown
Non-inverting differential clock input.
14
CLK
Input
Pullup
Inverting differential clock input.
15, 16
GND
Power
Power supply ground.
17
OEB
Input
Pullup
Output enable for QBx pins. When HIGH, QBx/QBx outputs are enabled.
When LOW, the QBx/QBx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels. See Table 3A.
18
F_SELB
Input
Pulldown
Frequency select pins for QBx/QBx outputs.
LVCMOS/LVTTL interface levels. See Table 3C.
A fixed precision resistor (RREF = 475
) from this pin to ground provides a
reference current used for differential current-mode QB0/nQB0 clock outputs.
19
IREF
Input
20, 21
QB0, QB0
Output
Differential output pair. HCSL interface levels.
23, 24
QB1, QB1
Output
Differential output pair. HCSL interface levels.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
C
IN
Input Capacitance
4
pF
R
PULLUP
Input Pullup Resistor
51
k
R
PULLDOWN
Input Pulldown Resistor
51
k
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