
87158AG
www.idt.com
REV. C JULY 25, 2010
10
ICS87158
1-TO-6, LVPECL-TO-HCSL/LVCMOS
÷1, ÷2, ÷4 CLOCK GENERATOR
SCHEMATIC EXAMPLE
Figure 3 shows an example of the ICS87158 LVPECL to
HCSL Clock Generator schematic.
In this example, the ICS87158 is configured as follows:
PWR_DWN# = 1
Mult_[1:0] = 10, Rref = 475
Ω, IREF = 2.32mA, I
OH = 6*IREF
SEL_[A,B,U] = 000, MREF = PECL
÷ 4, all HOST output = PECL ÷ 2
SEL_T = 0, Output Enable
Zo = 50
50MHz,
LVCMOS/LVTTL
C10
0.1uF
C10
0.1uF
Zo = 50
200MHz, 3.3V
LVPECL
ICS8431-11
(U1-13)
R2
50
3.3V LVPECL
R8
28
+
-
R4
50
(U1-19)
R9
28
Zo = 50
(U1-28)
(U1-40)
Zo = 50
(U1-14)
VDD=3.3V
(U1-23)
R5
50
C10
0.1uF
ICS9222-01_REFCLK
(U1-34)
C5
0.1uF
(U1-48)
ICS9222-01_REFCLK
C6
0.1uF
ICS8431-01
U1
85158
1
2
3
4
5
6
7
8
9
10
35
36
25
27
28
32
31
29
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
30
33
34
42
41
40
39
38
37
46
45
44
43
47
48
GND
VDD
VDD_R
PECL
nPECL
GND_R
VDD_M
MREF
nMREF
GND_M
HOST_N4
HOST_P4
VDD_I
IREF
VDD_H
HOST_N5
GND_H
HOST_N6
VDD
GND
VDD_L
VDD
GND_L
SEL_T
MULT_0
MULT_1
VDD_L
GND_L
SEL_A
SEL_B
SEL_U
PWR_DWN#
GND_I
HOST_P6
HOST_P5
VDD_H
HOST_P2
HOST_N2
VDD_H
HOST_P3
HOST_N3
GND_H
VDD_H
HOST_P1
HOST_N1
GND_H
VDD
C9
0.1uF
VDD=3.3V
C4
0.1uF
Zo = 50
100MHz,
HCSL
Rref
475
C3
0.1uF
C7
0.1uF
(U1-46)
C8
0.1uF
(U1-11)
C10
0.1uF
(U1-2)
(U1-25)
(U1-7)
C5
0.1uF
R6
33
C9
0.1uF
R1
50
VDD=3.3V
R7
33
R3
50
FIGURE 3. ICS87158 SCHEMATIC LAYOUT