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參數(shù)資料
| 型號： | ICS854S54AYI-08LF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 6/21頁 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFF MUX 2:1/1:2 64-TQFP |
| 標準包裝： | 160 |
| 系列： | HiPerClockS™ |
| 類型： | 扇出緩沖器（分配），多路復用器 |
| 電路數(shù)： | 8 |
| 比率 - 輸入:輸出： | 2:1，1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | LVDS |
| 頻率 - 最大： | 1.3GHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應商設(shè)備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 854S54AYI-08LF |
ICS854S54AYI-08 FEBRUARY 4, 2010
14
2010 Integrated Device Technology, Inc.
ICS854S54I-08 Data Sheet
OCTAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 3. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadframe Base Package, Amkor Technology.
Figure 3. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100
differential
transmission line environment, LVDS drivers require a matched load
termination of 100
across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
Figure 4. Typical LVDS Driver Termination
GROUND PLANE
LAND PATTERN
SOLDER
THERMAL VIA
EXPOSED HEAT SLUG
(GROUND PAD)
PIN
PIN PAD
SOLDER
PIN
PIN PAD
SOLDER
3.3V
LVDS Driver
R1
100
–
+
3.3V
50
50
100
Differential Transmission Line
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