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參數(shù)資料
| 型號： | ICS854S006AGILFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFF 1:6 1.7GHZ 24-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | HiPerClockS™ |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 輸出： | LVDS |
| 頻率 - 最大： | 1.7GHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 854S006AGILFT |
ICS854S006AGI REVISION B JANUARY 18, 2010
11
2010 Integrated Device Technology, Inc.
ICS854S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS854S006I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S006I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 55mA = 190.575mW
Power (outputs)
MAX
= V
DDO_MAX
* I
DDO_MAX
= 3.465V * 105mA = 363.825mW
Total Power
_MAX
= 190.575mW + 363.825mW = 554.4mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C
ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used.
Assuming no air flow and a multi-layer board, the appropriate value is 70°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.554W * 70°C/W = 123.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE
θθθθθ
JA
FOR
24-LEAD TSSOP, FORCED CONVECTION
θθθθθ
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
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