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參數(shù)資料
| 型號(hào)： | ICS85320AMIT |
| 英文描述： | LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR |
| 中文描述： | 的LVCMOS / LVTTL至差分為2.5V / 3.3V的LVPECL的譯者 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 198K |
| 代理商： | ICS85320AMIT |
85320AMI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 25, 2004
5
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V / 3.3V LVPECL T
RANSLATOR
A
DDITIVE
P
HASE
J
ITTER
Input/Output Additive Phase Jitter
@ 156.25MHz (12KHz to 20MHz)
= 0.05ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
S
H
O
Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS85320I | Replaced by SN74LS174 : 6-bit D-type positive-edge-triggered flip-flops with clear 16-PDIP 0 to 70 |
| ICS85322AM | DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V/3.3V LVPECL TRANSLATOR |
| ICS85322 | DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V/3.3V LVPECL TRANSLATOR |
| ICS85322AM-T | DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V/3.3V LVPECL TRANSLATOR |
| ICS8532AY-01 | LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS853210AYLF | 功能描述:IC CLOCK BUFFER 1:5 3GHZ 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復(fù)用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| ICS853210AYLFT | 功能描述:IC CLOCK BUFFER 1:5 3GHZ 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復(fù)用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| ICS85322AGILF | 制造商:Integrated Device Technology Inc 功能描述:IC TRANSLATOR LVPECL 8TSSOP |
| ICS85322AGILFT | 制造商:Integrated Device Technology Inc 功能描述:IC TRANSLATOR LVPECL 8TSSOP |
| ICS85322AMILF | 功能描述:IC TRANSLATOR LVPECL 8-SOIC RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- 邏輯功能:變換器，雙向 位數(shù):2 輸入類型:CMOS 輸出類型:CMOS 數(shù)據(jù)速率:16Mbps 通道數(shù):2 輸出/通道數(shù)目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應(yīng)商設(shè)備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
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