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參數(shù)資料
| 型號： | ICS85310AYI-01LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:10 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | HiPerClockS™ |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 輸出： | ECL，LVPECL |
| 頻率 - 最大： | 700MHz |
| 電源電壓： | 2.375 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 85310AYI-01LFT |
ICS85310AYI-01 REVISION I JANUARY 25, 2010
5
2010 Integrated Device Technology, Inc.
ICS5310I-01 Data Sheet
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Additive Phase Jitter, RMS
@ 155.52MHz = <0.13ps (typical)
SSB
Phas
e
N
o
ise
dBc/Hz
Offset from Carrier Frequency (Hz)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS85310AYI-01LN | 制造商:INT_CIR_SYS 功能描述: |
| ICS85310AYI-11LF | 功能描述:IC CLOCK BUFFER MUX 2:10 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS85310AYI-11LFT | 功能描述:IC CLOCK BUFFER MUX 2:10 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS85310AYI-21 | 制造商:INT_CIR_SYS 功能描述: |
| ICS85310AYI-21LN | 功能描述:IC CLK BUFFER 1:5 700MHZ 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
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