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| 型號： | ICS85211BMI-03LNT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER 1:2 700MHZ 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | HiPerClockS™ |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 輸出： | LVHSTL |
| 頻率 - 最大： | 700MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 85211BMI-03LNT |
ICS85211BMI-03 REVISION C MARCH 12, 2010
7
2010 Integrated Device Technology, Inc.
ICS85211BI-03 Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Application Information
Recommendations for Unused Output Pins
Outputs:
LVHSTL Outputs
All unused LVHSTL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the VREF in the center of the input voltage swing.
For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and
R2 value should be adjusted to set VREF at 1.25V. The values below
are for when both the single ended swing and VCC are at the same
voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50
applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
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