參數(shù)資料
型號(hào): ICS8516FYILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/18頁
文件大?。?/td> 0K
描述: IC CLK BUFF 1:16 700MHZ 48-LQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: HiPerClockS™
類型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:16
差分 - 輸入:輸出: 是/是
輸入: HCSL,LVDS,LVHSTL,LVPECL,SSTL
輸出: LVDS
頻率 - 最大: 700MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
其它名稱: 8516FYILFT
ICS8516I REVISION B SEPTEMBER 10, 2009
13
2009 Integrated Device Technology, Inc.
ICS8516I Data Sheet
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8516I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8516I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Power_
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 185mA = 641mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature for HiPerClockS
TM devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming no air
flow of and a multi-layer board, the appropriate value is 47.9°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.641W * 47.9°C/W = 115.7°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (multi-layer).
TABLE 6. THERMAL RESISTANCE
θθθθθ
JA
FOR
48-PIN LFQP, FORCED CONVECTION
θθθθθ
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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