FEMTOCLOCK
參數(shù)資料
型號: ICS844071AGLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 14/14頁
文件大?。?/td> 0K
描述: IC CLK GEN SAS LVDS 8-TSSOP
標準包裝: 96
系列: HiPerClockS™, FemtoClock™
類型: 時鐘發(fā)生器
PLL:
輸入: 晶體
輸出: LVDS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/是
頻率 - 最大: 170MHz
除法器/乘法器: 是/是
電源電壓: 2.375 V ~ 3.63 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 8-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 1250 (CN2011-ZH PDF)
其它名稱: 800-1148
800-1148-5
800-1148-ND
844071AGLF
ICS844071AG REVISION B OCTOBER 10, 2012
9
2012 Integrated Device Technology, Inc.
ICS844071 Data Sheet
FEMTOCLOCK CRYSTAL-TO-LVDS CLOCK GENERATOR
Crystal Input Interface
The ICS844071 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in Figure
2 below were determined using a 25MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum C1
and C2 values can be slightly adjusted for different board layouts.
Figure 2. Crystal Input Interface
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100
parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 3A can be used
with either type of output structure. Figure 3B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS Termination
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
33p
C2
22p
LVDS
Driver
LVDS
Driver
LVDS
Receiver
LVDS
Receiver
ZT
C
ZO ≈ ZT
ZT
2
ZT
2
Figure 3A. Standard Termination
Figure 3B. Optional Termination
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