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參數(shù)資料
| 型號： | ICS844003BG-01LF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER 3LVDS 24-ETSSOP |
| 產(chǎn)品培訓(xùn)模塊： | PCI-Express |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:3 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 680MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 844003BG-01LF |
ICS844003-01
FEMTOCLOCKSCRYSTAL-TO- LVDS FREQUENCY SYNTHESIZER
IDT / ICS LVDS FREQUENCY SYNTHESIZER
2
ICS844003BG-01 REV. A AUGUST 21, 2008
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number
Name
Type
Description
1,
24
DIV_SELB0,
DIV_SELB1
Input
Pullup
Division select pin for Bank B. Default = HIGH.
LVCMOS/LVTTL interface levels. See Table 3B.
2
VCO_SEL
Input
Pullup
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
REF_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
3
MR
Input
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. Has an
internal pulldown resistor so the power-up default state of outputs and dividers
are enabled. LVCMOS/LVTTL interface levels.
4VDDO_A
Power
Output supply pin for Bank A outputs.
5, 6
QA0, nQA0
Output
Differential output pair. LVDS interface levels.
7
OEB
Input
Pullup
Output enable Bank B. Active High outputs are enable. When logic HIGH, the
output pairs on Bank B are enabled. When logic LOW, the output pairs are in a
high impedance state. Has an internal pullup resistor so the default power-up
state of outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3E.
8
OEA
Input
Pullup
Output enable Bank A. Active High output enable. When logic HIGH, the output
pair in Bank A is enabled. When logic LOW, the output pair is in a high
impedance state. Has an internal pullup resistor so the default power-up state of
output is enabled. LVCMOS/LVTTL interface levels. See Table 3D.
9
FB_DIV
Input
Pulldown
Feedback divide select. When Low (default), the feedback divider is set for ÷25.
When HIGH, the feedback divider is set for ÷32. See Table 3C.
LVCMOS/LVTTL interface levels.
10
VDDA
Power
Analog supply pin.
11
VDD
Power
Core supply pin.
12,
13
DIV_SELA0,
DIV_SELA1
Input
Pullup
Division select pin for Bank A. Default = HIGH. See Table 3A.
LVCMOS/LVTTL interface levels.
14
GND
Power
Power supply ground.
15,
16
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit
with a single-ended reference clock.
17
REF_CLK
Input
Pulldown
Single-ended reference clock input. Has an internal pulldown resistor to pull to
low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
18
XTAL_SEL
Input
Pullup
Crystal select pin. Selects between the single-ended REF_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
19, 20
nQB1, QB1
Output
Differential output pair. LVDS interface levels.
21, 22
nQB0, QB0
Output
Differential output pair. LVDS interface levels.
23
VDDO_B
Power
Output supply pin for Bank B outputs.
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