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ICS843SDN
FEMTOCLOCKCRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
IDT / ICS 3.3V LVPECL CLOCK GENERATOR
6
ICS843SDNAG REV. A
NOVEMBER 13, 2012
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS843SDN pro-
vides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VCC and VCCA should be indi-
vidually connected to the power supply plane through vias, and
0.01F bypass capacitors should be used for each pin. Figure 1 il-
lustrates this for a generic VCC pin and also shows that VCCA re-
quires that an additional 10
resistor along with a 10F bypass
capacitor be connected to the VCCA pin.
Figure 1. Power Supply Filtering
Crystal Input Interface
The ICS843SDN has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
Figure 2. Crystal Input Interface
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gener-
ate ECL/LVPECL compatible outputs. Therefore, terminating resis-
tors (DC current path to ground) or current sources must be used
for functionality. These outputs are designed to drive 50
transmis-
sion lines. Matched impedance techniques should be used to max-
imize operating frequency and minimize signal distortion. Figures
4A and 4B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it would
be recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component pro-
cess variations.
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
VCC
VCCA
3.3V
10
Ω
10F
.01F
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27pF
C2
27pF
3.3V
V
CC - 2V
R1
50
Ω
R2
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
+
_
RTT =
* Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL
Input
R1
84
Ω
R2
84
Ω
3.3V
R3
125
Ω
R4
125
Ω
Z
o = 50Ω
Z
o = 50Ω
LVPECL
Input
3.3V
+
_
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