參數(shù)資料
型號(hào)： ICS843246BGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： XO, clock
英文描述： FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
中文描述： 340 MHz, OTHER CLOCK GENERATOR, PDSO24
封裝： 4.40 X 7.80 MM, 0.90 MM HEIGHT, MO-153, TSSOP-24
文件頁數(shù)： 9/17頁
文件大小： 345K
代理商： ICS843246BGI
IDT
/ ICS
3.3V LVPECL FREQUENCY SYNTHESIZER
9
ICS843246BGI REV. A AUGUST 2, 2007
ICS843246I
FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
V
CC
- 2V
50
Ω
50
Ω
RTT
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
drive 50
Ω
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 3A and 3B
show two different layouts
which are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended that the
board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
LVCMOS
TO
XTAL I
NTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in
Figure X.
The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
F
IGURE
3. G
ENERAL
D
IAGRAM
FOR
LVCMOS D
RIVER
TO
XTAL I
NPUT
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
Ω
applications, R1
and R2 can be 100
Ω
. This can also be accomplished by removing
R1 and making R2 50
Ω
.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
相關(guān)PDF資料
PDF描述
ICS843246BGILF FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICS843246BGILFT FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICS843246BGIT FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICS843246I FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICS844001-21 FEMTOCLOCKS⑩ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS843246BGILF 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICS843246BGILFT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICS843246BGIT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICS843246I 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICS84324EM 制造商:ICS 制造商全稱:ICS 功能描述:CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
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