參數(shù)資料
型號: ICS8431CM-11
英文描述: 255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
中文描述: 255MHZ,低抖動LVPECL的頻率合成器
文件頁數(shù): 8/11頁
文件大?。?/td> 2083K
代理商: ICS8431CM-11
ICS8431CM-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 5, 2001
8
ICS8431-01
200MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
T
ERMINATION
FOR
PECL O
UTPUTS
The clock layout topology shown below is typical for
IA64/32 platforms. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/PECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
5B. LVPECL O
UTPUT
T
ERMINATION
3.3V
FOUT
FIN
5
2Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
Z
o
= 50
Z
o
= 50
F
IGURE
5A. LVPECL O
UTPUT
T
ERMINATION
RTT =
1
(VOH + VOL / VCC
2)
2
Z
o
Z
o
= 50
Z
o
= 50
50
50
RTT
VCC-2V
FIN
FOUT
Z
o
= 50
Z
o
= 50
F
IGURE
6A. R
ECOMMENDED
S
CHEMATIC
L
AYOUT
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. There are a few simple termination
schemes. Figures 5A and 5B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
L
AYOUT
G
UIDELINE
The schematic of the ICS8431-01 layout example used in this layout guideline is shown in Figure 6A.The ICS8431-01 recommended
PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual
system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of
the P.C. board.
R3
125
C3
X1
U1
8431-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
nc
nc
nc
nc
nc
nc
nc
nc
nc
SSC_CTL0
SSC_CTL1
VEE
TEST_IO
VDD
VEE
nFOUT
FOUT
VDDO
nc
nc
VEE
VDDA
nc
nc
nc
VDDI
XTAL2
XTAL1
C1
0.1uF
VDDA
IN+
VDD
IN-
C4
R4
84
R2
84
R1
50
IN+
VDD
R2
50
R5
10
C6
0.01uF
R3
50
R1
125
VDD
TL2
Zo = 50 Ohm
IN-
VDD0
Termination A
TL1
Zo = 50 Ohm
C2
Termination
B (not shown
in the layout)
相關(guān)PDF資料
PDF描述
ICS8431CM-11T 255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
ICS843101-312 FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843101AG-312 FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843101AG-312LF FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843101AG-312LFT FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
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